US 6,982,445 B2 | ||
MRAM architecture with a bit line located underneath the magnetic tunneling junction device | ||
David Tsang, Cupertino, Calif. (US) | ||
Assigned to Applied Spintronics Technology, Inc., Cupertino, Calif. (US) | ||
Filed on Oct. 16, 2003, as Appl. No. 10/688,250. | ||
Claims priority of provisional application 60/467529, filed on May 05, 2003. | ||
Prior Publication US 2004/0222450 A1, Nov. 11, 2004 | ||
Int. Cl. H01L 29/76 (2006.01) |
U.S. Cl. 257—295 | 13 Claims |
1. A magnetic memory comprising:
a plurality of magnetic elements, each of the plurality of magnetic elements having a top and a bottom;
at least a first write line connected to the bottom of each of a first portion of the plurality of magnetic elements;
at least a second write line residing above the top of a second portion of the plurality of magnetic elements, the at least
the second write line being electrically insulated from each of the second portion of the plurality of magnetic elements,
the at least the first write line and/or the at least the second write line being a magnetic write line including a magnetic
material in a core portion of the magnetic write line;
a plurality of conductive plugs for electrically coupling to the plurality of magnetic elements, the plurality of conductive
plugs configured such that no portion of the plurality of conductive plugs resides directly below the plurality of magnetic
elements.
|