US 6,982,578 B2 | ||
Digital delay-locked loop circuits with hierarchical delay adjustment | ||
Seong-hoon Lee, Boise, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Nov. 26, 2003, as Appl. No. 10/722,959. | ||
Prior Publication US 2005/0110539 A1, May 26, 2005 | ||
Int. Cl. H03L 7/06 (2006.01) |
U.S. Cl. 327—158 | 37 Claims |
1. A method of signal delay adjustment comprising:
receiving a first input signal having a first phase and a second input signal having a second phase;
receiving a first control signal, a second control signal, and a third control signal;
generating a first signal having a third phase between said first phase and said second phase, said third phase determined
by said first control signal;
generating a second signal having a fourth phase between said first phase and said second phase, said fourth phase determined
by said second control signal; and
generating a third signal having a fifth phase between said third phase and said fourth phase, said fifth phase determined
by said third control signal.
|