US 6,982,589 B2 | ||
Multi-stage multiplexer | ||
Venkat S. Veeramachaneni, Hillsboro, Oreg. (US); and Dinesh Somasekhar, Hillsboro, Oreg. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Feb. 28, 2001, as Appl. No. 9/796,072. | ||
Prior Publication US 2002/0118708 A1, Aug. 29, 2002 | ||
Int. Cl. H03K 17/62 (2006.01) |
U.S. Cl. 327—408 | 22 Claims |
1. A multiplexer comprising:
a first stage including tri-state buffers, each of which has split outputs;
a final stage including a tri-state buffer having an output; and
circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to
the output of the final-stage buffer;
wherein the split outputs of the first-stage buffers are coupled directly to inputs of the final-stage buffer.
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