US 6,983,015 B1 | ||
Signal processor | ||
Nicholas Ian Saunders, Basingstoke (United Kingdom); and Robert Mark Stefan Porter, Maidenhead (United Kingdom) | ||
Assigned to Sony United Kingdom Limited, Weybridge (United Kingdom) | ||
Filed on Aug. 24, 2000, as Appl. No. 9/645,748. | ||
Claims priority of application No. 9920274 (GB), filed on Aug. 26, 1999. | ||
Int. Cl. H04N 7/12 (2006.01) |
U.S. Cl. 375—240.1 | 40 Claims |
1. A signal processor for splicing a compressed bitstream B0 to a compressed bitstream A0, the bitstreams A0 and B0 comprising bits representing one or more pictures the signal processor comprising:
a decoder for decoding the bitstreams A0 and B0;
a switch coupled to the decoder for producing a spliced bitstream S, comprising data from bitstream B0 spliced to data from bitstream A0 at a splice point; and
an encoder for re-encoding the spliced bitstream S to form a re-encoded spliced bitstream C for supply to a downstream decoder
having a downstream buffer an occupancy of such a downstream buffer being dependent upon the number of bits with which pictures
of the spliced bitstream S are re-encoded by the encoder,
wherein the encoder is controlled over a transitional region to allocate a number of bits with which to re-encode a picture
of the spliced bitstream S in the transitional region in dependence upon a target downstream buffer occupancy for the bitstream
B0) and a downstream buffer occupancy for the re-encoded spliced bitstream C, so that the downstream buffer occupancy of the
downstream buffer varies over the transitional region from the downstream buffer occupancy for bitstream A0 to the downstream buffer occupancy for bitstream B0 according to a path in which the rate of change of downstream buffer occupancy is limited to a predetermined maximum rate.
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