US 6,982,200 B2 | ||
Semiconductor device manufacturing method | ||
Junji Noguchi, Tokyo (Japan); Toshinori Imai, Ome (Japan); and Tsuyoshi Fujiwara, Hamura (Japan) | ||
Assigned to Renesas Technology Corporation, Tokyo (Japan) | ||
Filed on Dec. 31, 2003, as Appl. No. 10/748,286. | ||
Claims priority of application No. P2003-002249 (JP), filed on Jan. 08, 2003. | ||
Prior Publication US 2004/0152256 A1, Aug. 05, 2004 | ||
Int. Cl. H01L 21/8242 (2006.01) |
U.S. Cl. 438—253 | 10 Claims |
1. A semiconductor device manufacturing method comprising the steps of:
(a) preparing a semiconductor substrate;
(b) forming, on said semiconductor substrate, a first insulation film where a first interconnect with a copper-based first
conductor film and a capacitor bottom electrode are buried;
(c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode
are buried;
(d) forming a third insulation film on said second insulation film;
(e) forming a first hole by removing a selected area of said third insulation film;
(f) forming a capacitor top electrode with a second conductor film in said first hole;
(g) forming a fourth insulation film on said third insulation film where said top electrode is buried;
(h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation
film, and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film
and said second insulation film at the bottom of said second hole; and
(i) filling a copper-based third conductor film into said second hole, said third hole, and said fourth hole.
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