US 6,982,201 B2
Structure and fabricating method with self-aligned bit line contact to word line in split gate flash
Chia Ta Hsieh, Tainan (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (Taiwan)
Filed on Oct. 13, 2004, as Appl. No. 10/964,391.
Application 10/964391 is a continuation of application No. 10/224215, filed on Aug. 20, 2002, granted, now 6,858,494.
Prior Publication US 2005/0048721 A1, Mar. 03, 2005
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—257 3 Claims
OG exemplary drawing
 
1. A method of forming a structure for split gate flash memory comprising:
providing a semiconductor substrate comprising split gate structures and drain surfaces, where a first insulator layer is formed over the split gate structures;
forming doped polysilicon spacer regions between the split gate structures and the drain surfaces;
oxidizing the drain surfaces to form a second insulator layer and oxidizing surfaces of the doped polysilicon spacer regions to form a third insulator layer, wherein the thickness of the second insulator layer is thinner than the third insulator layer;
removing the second insulator layer over the drain surfaces;
implanting ions into the drain surfaces to form drain regions; and
forming a conductive layer over the drain regions.