US 6,982,223 B2 | ||
Method of manufacturing a semiconductor device | ||
Ju-Wan Kim, Seoul (Korea, Republic of); Shin-Hye Kim, Yongin-si (Korea, Republic of); Ju-Bum Lee, Yongin-si (Korea, Republic of); and Hyong-Soo Kim, Suwon-si (Korea, Republic of) | ||
Assigned to Samsung Electronics, Co., Ltd., Suwon (Korea, Republic of) | ||
Filed on Apr. 15, 2003, as Appl. No. 10/413,944. | ||
Claims priority of application No. 2002-45897 (KR), filed on Aug. 02, 2002. | ||
Prior Publication US 2004/0038516 A1, Feb. 26, 2004 | ||
Int. Cl. H01L 21/4763 (2006.01); H01L 21/31 (2006.01) |
U.S. Cl. 438—632 | 13 Claims |
1. A method of manufacturing a semiconductor device comprising:
forming a plurality of conductive patterns on a substrate;
forming a capping insulation layer on said conductive patterns;
plasma treating said capping insulation layer, wherein said capping insulation layer is a SiN layer, and wherein a gas used
for said plasma treating comprises NH3, Ar, H2, or any combination thereof; and
depositing an interlayer dielectric material on said plasma treated capping insulation layer and reflowing the interlayer
dielectric material, wherein the plasma treating and reflowing substantially prevent formation of voids of the interlayer
dielectric material in gaps between the conductive patterns.
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