US 6,982,706 B1 | ||
Liquid crystal driving circuit, semiconductor integrated circuit device, reference voltage buffering circuit, and method for controlling the same | ||
Yasuyuki Doi, Nagaokakyo (Japan); Tetsuro Oomori, Hirakata (Japan); and Kazuyoshi Nishi, Muko (Japan) | ||
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan) | ||
Appl. No. 10/19,437 PCT Filed Aug. 31, 2000, PCT No. PCT/JP00/05904 § 371(c)(1), (2), (4) Date Dec. 31, 2001, PCT Pub. No. WO01/45079, PCT Pub. Date Jun. 21, 2001. |
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Claims priority of application No. 11-356898 (JP), filed on Dec. 16, 1999. | ||
Int. Cl. G09G 5/00 (2006.01) |
U.S. Cl. 345—206 | 23 Claims |
7. A liquid crystal driving circuit for driving a liquid crystal element on a liquid crystal panel, the liquid crystal driving
circuit comprising:
a plurality of source driver circuit devices on the liquid crystal panel, each source driver circuit device including:
a plurality of input-side pads, each input-side pad receiving a reference voltage;
a plurality of output-side pads, each output-side pad outputting the reference voltage;
a plurality of in-chip reference voltage wires, each in-chip reference voltage wire directly connecting each input-side pad
to each output-side pad to transmit the reference voltage;
a plurality of branch reference voltage wires, each branch reference voltage wire branching off from each in-chip reference
voltage wire and transmitting the reference voltage in parallel with each in-chip reference voltage wire;
a plurality of buffers, each buffer coupled to each branch reference voltage wire and outputting an output voltage in response
to the reference voltage transmitted by each branch reference voltage wire and capable of preventing an electric current from
flowing via each branch reference voltage wire; and
a selection circuit selecting a voltage for driving the liquid crystal element in response to output voltages of the plurality
of buffers,
a plurality of inter-chip reference voltage wire units, each inter-chip reference voltage wire unit interposed between any
two adjacent source driver circuit devices of the plurality of source driver circuit devices and including a plurality of
inter-chip reference voltage wires, each inter-chip reference voltage wire connecting each output-side pad of one source driver
circuit device of the two adjacent source driver circuit devices to each input-side pad of the other source driver circuit
device of the two adjacent source driver circuit devices;
a reference voltage production circuit capable of producing a plurality of reference voltages to drive the plurality of source
driver circuit devices; and
a reference voltage providing wire unit capable of receiving the plurality of reference voltages and providing the plurality
of reference voltages to one of the plurality of source driver circuit devices and including a plurality of reference voltage
providing wires, each reference voltage providing wire coupled to each in-chip reference voltage wire via each input-side
pad of the one of the plurality of source driver circuit devices to provide a reference voltage.
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