US 6,982,476 B2
Integrated circuit feature layout for improved chemical mechanical polishing
James M. Cleeves, Redwood City, Calif. (US); and Michael A. Vyvoda, Fremont, Calif. (US)
Assigned to Matrix Semiconductor, Santa Clara, Calif. (US)
Filed on Mar. 12, 2004, as Appl. No. 10/800,078.
Application 10/800078 is a division of application No. 09/935862, filed on Aug. 22, 2001, granted, now 6,730,931.
Application 09/935862 is a division of application No. 09/775761, filed on Feb. 02, 2001, granted, now 6,486,066.
Prior Publication US 2004/0173904 A1, Sep. 09, 2004
Int. Cl. H01L 23/544 (2006.01); H01L 29/73 (2006.01)
U.S. Cl. 257—620 7 Claims
OG exemplary drawing
 
1. A level of an integrated circuit comprising:
a core area having a 25 μm2 area, said core area having a first density of features wherein said first density of features is the total area of features in the core area divided by the total core area; and
a peripheral area adjacent to said core area and having a 25 μm2 area, said peripheral area having a second density of features wherein said second density is the total area of features in the peripheral area divided by the total peripheral area, wherein said second density is substantially similar to said first density.