US 6,982,921 B2 | ||
Multiple configuration multiple chip memory device and method | ||
Donald M. Morgan, Meridian, Id. (US); and Todd A. Merritt, Boise, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Oct. 08, 2004, as Appl. No. 10/961,576. | ||
Application 10/961576 is a division of application No. 10/355781, filed on Jan. 29, 2003, granted, now 6,882,590, filed on Apr. 19, 2005. | ||
Prior Publication US 2005/0083763 A1, Apr. 21, 2005 | ||
Int. Cl. G11C 8/00 (2006.01) |
U.S. Cl. 365—230.03 | 13 Claims |
1. A method of using a memory integrated circuit having an internal row address bus for receiving M row address bits and an
internal column address bus for receiving N column address bits, comprising:
in a first use for the memory integrated circuit:
packaging one of the memory integrated circuits in an integrated circuit package;
coupling M externally applied row address bits to the integrated circuit package;
coupling N externally applied column address bits to the integrated circuit package;
coupling the M externally applied row address bits to the internal row address bus of the memory integrated circuit; and
coupling the N externally applied column address bits to the internal column address bus of the memory integrated circuit;
and
in a second use for the memory integrated circuit:
packaging at least two of the memory integrated circuits in a single integrated circuit package;
coupling M+P externally applied row address bits to the integrated circuit package;
coupling N externally applied column address bits to the integrated circuit package;
coupling M of the M+P externally applied row address bits to the internal row address bus of each of the memory integrated
circuits; and
coupling the N externally applied column address bits and P of the M+P externally applied row address bits to the internal
column address bus of each of the memory integrated circuits.
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