US 6,982,583 B2 | ||
Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process | ||
Guangming Yin, Foothill Ranch, Calif. (US); Ichiro Fujimori, Irvine, Calif. (US); and Armond Hairapetian, Newport Coast, Calif. (US) | ||
Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
Filed on Jun. 25, 2004, as Appl. No. 10/876,790. | ||
Application 10/876790 is a continuation of application No. 10/229257, filed on Aug. 26, 2002, granted, now 6,897,697. | ||
Application 10/229257 is a continuation in part of application No. 10/143087, filed on May 09, 2002, granted, now 6,900,670. | ||
Application 10/143087 is a continuation of application No. 09/484856, filed on Jan. 18, 2000, granted, now 6,424,194. | ||
Claims priority of provisional application 60/141355, filed on Jun. 28, 1999. | ||
Prior Publication US 2004/0227544 A1, Nov. 18, 2004 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H03K 3/356 (2006.01) |
U.S. Cl. 327—210 | 20 Claims |
1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential
input signals, the first circuitry is operable to process a first signal thereby generating a second signal;
second circuitry coupled to the first circuitry and implemented using conventional complementary metal-oxide-semiconductor
(CMOS) logic wherein substantially zero static current is dissipated, the second circuitry is operable to process the second
signal thereby generating a third signal;
wherein the first circuitry is coupled to a first power supply voltage;
wherein the second circuitry is coupled to a second power supply voltage that is different than the first power supply voltage;
and
wherein the first power supply voltage is higher in magnitude than the second power supply.
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