US 6,982,917 B2 | ||
DRAM partial refresh circuits and methods | ||
Yun-sang Lee, Kyungki-do (Korea, Republic of); and Won-chang Jung, Kyungki-do (Korea, Republic of) | ||
Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
Filed on Jul. 10, 2002, as Appl. No. 10/192,406. | ||
Claims priority of application No. 2001-68841 (KR), filed on Nov. 06, 2001. | ||
Prior Publication US 2003/0086325 A1, May 08, 2003 | ||
Int. Cl. G11C 7/00 (2006.01) |
U.S. Cl. 365—222 | 9 Claims |
4. A refresh circuit in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations
in the memory bank, the word lines subdivided into first and second groups of subword lines, the refresh circuit comprising:
a delay circuit which receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later;
a first driving circuit which responds to the refresh signal by driving word lines in the first group of subword lines; and
a second driving circuit which responds to the delayed refresh signal by driving word lines in the second group of subword
lines, wherein the first and second groups of subword lines both correspond to a same predetermined row address in the memory
bank.
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