US 6,982,904 B2
Non-volatile semiconductor memory device and electric device with the same
Hitoshi Shiga, Matsuyama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Jun. 01, 2004, as Appl. No. 10/856,851.
Claims priority of application No. 2004-002041 (JP), filed on Jan. 07, 2004.
Prior Publication US 2005/0146959 A1, Jul. 07, 2005
Int. Cl. G11C 16/06 (2006.01)
U.S. Cl. 365—185.09 16 Claims
OG exemplary drawing
 
1. A non-volatile semiconductor memory device comprising:
a cell array having electrically rewritable and non-volatile memory cells arranged therein; and
a sense amplifier circuit configured to detect voltage change of a bit line in said cell array, thereby reading data of a selected memory cell coupled to the bit line, wherein
said sense amplifier circuit is controlled to read data at plural timings within a period in which the bit line voltage is changing in correspondence with said selected memory cell, and compare data read out by successive two data read operations with each other so as to judge a threshold margin of said selected memory cell.