US 6,982,456 B2 | ||
Nonvolatile semiconductor memory device and method for fabricating the same | ||
Nobuyo Sugiyama, Hyogo (Japan); Hiromasa Fujimoto, Kyoto (Japan); Shinji Odanaka, Osaka (Japan); and Seiki Ogura, Wappingers Falls, N.Y. (US) | ||
Assigned to Matsushita Electic Industrial Co., Ltd., Osaka (Japan) | ||
Filed on Jul. 13, 2004, as Appl. No. 10/889,013. | ||
Application 10/889013 is a division of application No. 10/366420, filed on Feb. 14, 2003, granted, now 6,770,931. | ||
Application 10/366420 is a division of application No. 09/902942, filed on Jul. 12, 2001, granted, now 6,538,275. | ||
Claims priority of application No. 2000-210887 (JP), filed on Jul. 12, 2000. | ||
Prior Publication US 2004/0246803 A1, Dec. 09, 2004 | ||
Int. Cl. H01L 29/76 (2006.01); H01L 29/788 (2006.01) |
U.S. Cl. 257—314 | 7 Claims |
1. A nonvolatile semiconductor memory device comprising:
a stepped portion formed in a semiconductor substrate, the stepped portion being composed of a first surface region serving
as an upper stage, a second surface region serving as a lower stage, and a step side region connecting the upper and lower
stages;
a first insulating film formed on the first surface region;
a control gate electrode formed on an area of the first surface region with the first insulating film interposed therebetween;
a floating gate electrode formed on the semiconductor substrate so as to cover up the stepped portion, the floating gate electrode
being capacitively coupled to a side surface of the control gate electrode closer to the stepped portion with a second insulating
film interposed therebetween and opposed to the second surface region and the step side region with a third insulating film
interposed therebetween;
a source region formed in an area of the first surface region opposite to the floating gate electrode relative to the control
gate electrode;
a drain region formed in an area of the second surface region underlying the floating gate electrode; and
an impurity region formed in the first surface region and step side region of the semiconductor substrate to have an impurity
concentration higher than an impurity concentration of the semiconductor substrate and a conductivity type opposite to a conductivity
type of the drain region,
wherein the impurity region is in contact with the third insulating film formed on the step side region.
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