US 6,982,458 B2 | ||
Method of making the selection gate in a split-gate flash EEPROM cell and its structure | ||
Wen-Ting Chu, Kaohsiung (Taiwan); Jack Yeh, Chu Pei (Taiwan); and Chrong-Jung Lin, Taipei (Taiwan) | ||
Assigned to Taiwan Semiconductor Maufacturing Co., LTD, Hsin-Chu (Taiwan) | ||
Filed on Aug. 31, 2004, as Appl. No. 10/929,397. | ||
Application 10/929397 is a division of application No. 10/355134, filed on Jan. 31, 2003, granted, now 6,787,418. | ||
Claims priority of application No. 91102132 A (TW), filed on Feb. 06, 2002. | ||
Prior Publication US 2005/0026368 A1, Feb. 03, 2005 | ||
Int. Cl. H01L 29/788 (2006.01) |
U.S. Cl. 257—316 | 5 Claims |
1. A split-gate flash EEPROM cell structure comprising:
a suspending gate structure, which is formed on a semiconductor substrate and is stacked, from bottom to top, with a gate
oxide layer, a polysilicon layer, and a first oxide layer,
the semiconductor substrate on one side of the suspending gate structure having a trench;
an inter polysilicon dielectric layer, which is formed on the sidewall of the suspending gate structure and the trench;
a polysilicon spacer, which is formed on the sidewall of the inter polysilicon dielectric layer as a selection gate;
a drain, which is formed on the semiconductor substrate in the trench, the drain being adjacent to the selection gate; and
a source, which is formed on the semiconductor substrate opposite to the trench.
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