US 6,983,441 B2
Embedding a JTAG host controller into an FPGA design
Douglas Albert Wescott, Adamstown, Md. (US)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Jun. 28, 2002, as Appl. No. 10/183,902.
Prior Publication US 2004/0001432 A1, Jan. 01, 2004
Int. Cl. H03K 19/00 (2006.01); G06F 17/50 (2006.01); G01R 31/28 (2006.01)
U.S. Cl. 716—17 12 Claims
OG exemplary drawing
 
1. A system for configuring a field programmable gate array (FPGA) as a peripheral Joint Test Access Group (JTAG) host controller for a peripheral hardware target, comprising:
a processor that includes source code for a JTAG host controller;
an FPGA attached to a peripheral printed circuit board, the FPGA including:
a memory array that is programmed with the source code for the JTAG host controller, by the external processor;
a processor core; and
JTAG interface logic;
a serial connector that connects the processor to the FPGA; and
a hardware target that is JTAG-compliant and attached to the peripheral printed circuit board;
wherein the FPGA sends JTAG host controller signals through the JTAG interface logic to the hardware target.