US 6,982,466 B2 | ||
Semiconductor devices including a silicide layer | ||
Hiroaki Tsugane, Sakata (Japan); and Hisakatsu Sato, Sakato (Japan) | ||
Assigned to Seiko Epson Corporation, Tokyo (Japan) | ||
Filed on Mar. 22, 2004, as Appl. No. 10/805,334. | ||
Application 10/805334 is a division of application No. 09/759665, filed on Jan. 13, 2001, granted, now 6,753,226. | ||
Claims priority of application No. 2000-5042 (JP), filed on Jan. 13, 2000. | ||
Prior Publication US 2004/0173833 A1, Sep. 09, 2004 | ||
Int. Cl. H01L 21/20 (2006.01) |
U.S. Cl. 257—382 | 10 Claims |
2. A semiconductor device comprising:
a DRAM located in a memory cell region;
a first field effect transistor that is located in a peripheral circuit region and becomes a component of a peripheral circuit
for the DRAM; and
a second field effect transistor located in a region other than the memory cell region and the peripheral circuit region,
wherein silicide layers are formed at a cell plate that is a component of a capacitor of the DRAM and at a source/drain of
the second field effect transistor, and
silicide layers are not formed at a source/drain that is a component of a memory cell selection field effect transistor of
the DRAM or at a source/drain of the first field effect transistor.
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