US 6,982,577 B2 | ||
Power-on reset circuit | ||
Yoshimasa Sekino, Tokyo (Japan); and Shoji Kitazawa, Tokyo (Japan) | ||
Assigned to Oki Electric Industry, Co., Ltd., Tokyo (Japan) | ||
Filed on Mar. 30, 2004, as Appl. No. 10/811,836. | ||
Claims priority of application No. 2003-384523 (JP), filed on Nov. 14, 2003. | ||
Prior Publication US 2005/0104635 A1, May 19, 2005 | ||
Int. Cl. H03L 17/22 (2006.01) |
U.S. Cl. 327—143 | 7 Claims |
1. A power-on reset circuit comprising:
a first capacitor connected between a power supply line and a first node;
a first MOS transistor connected between said first node and a second node, and ON/OFF controlled based on a first pulse signal;
a second MOS transistor connected between said second node and a reference potential, and ON/OFF controlled based on a second
pulse signal;
a second capacitor connected between said second node and said reference potential;
a timing control unit for generating said first and second pulse signals in synchronism with a clock signal externally applied
thereto; and
an output portion outputting a reset signal when the potential of an internal node decreases below a threshold voltage after
the application of a power supply voltage to said power supply line.
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