US 6,983,435 B2 | ||
Integrated design verification and design simplification system | ||
Jason Raymond Baumgartner, Austin, Tex. (US); Hari Mony, Austin, Tex. (US); and Viresh Paruthi, Austin, Tex. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Jun. 19, 2003, as Appl. No. 10/464,883. | ||
Prior Publication US 2004/0261043 A1, Dec. 23, 2004 | ||
Int. Cl. G06F 17/50 (2006.01); G06F 9/45 (2006.01) |
U.S. Cl. 716—5 | 22 Claims |
1. An integrated design verification process, comprising:
performing under approximation verification (UAV) processing using a design model of the integrated circuit;
extracting and storing coverage data generated by the UAV process;
responsive to the UAV processing failing to resolve a verification problem, performing over approximation verification (OAV)
processing on the design model;
responsive to the OAV processing failing to resolve the verification problem, evaluating a previously defined lighthouse,
wherein the lighthouse is indicative of a defined state being achieved during the verification processing; and
responsive to a lighthouse being disproven, storing at least one state disproving the lighthouse to use as a seed state for
subsequent UAV processing and, responsive to a lighthouse being proven, simplifying the design model before subsequent verification
processing by eliminating at least one latch from the design model.
|