US 6,982,592 B2
Zero if complex quadrature frequency discriminator and FM demodulator
Branislav A. Petrovic, La Jolla, Calif. (US); and Maxim Ashkenasi, La Jolla, Calif. (US)
Assigned to Broadband Innovations, Inc., San Diego, Calif. (US)
Filed on Dec. 07, 2004, as Appl. No. 11/4,992.
Application 11/004992 is a continuation of application No. 09/872143, filed on Jun. 01, 2001, granted, now 6,847,255.
Prior Publication US 2005/0096000 A1, May 05, 2005
This patent is subject to a terminal disclaimer.
Int. Cl. H03D 3/00 (2006.01); H03D 13/00 (2006.01); H03L 7/087 (2006.01)
U.S. Cl. 329—323 30 Claims
OG exemplary drawing
 
1. A method for providing frequency discrimination/comparison using complex single side-band (SSB) down conversion to zero intermediate frequency (IF), comprising:
receiving a bi-level digital local clock signal having a dominant frequency component Fref for division by four into a frequency component Fref/4 such that a plurality of components of that frequency are produced including an in-phase component Iref and a quadrature component Qref;
receiving a bi-level digital input signal having a dominant frequency component Fin for division by four into a frequency component Fin/4 such that a plurality of digital components of that frequency are produced including an in-phase component Iin and a quadrature component Qin;
producing a plurality of digital signals using said in-phase component Iref, said quadrature component Qref, said in-phase component Iin, and said quadrature component Qin, wherein said plurality of digital signals have a dominant frequency that is substantially equal to a frequency difference Fref/4−Fin/4, and one of said plurality of digital signals is an in-phase component I(t) and another of said plurality of digital signals is a quadrature component Q(t);
delaying each of said in-phase component I(t) and quadrature component Q(t) digital signals by substantially the same time delay τ to provide respective delayed digital signals I(t−τ) and Q(t−τ);
performing a bi-level operation on said in-phase delayed digital signal I(t−τ) with said quadrature component Q(t), and performing a complementary bi-level operation on said quadrature delayed digital signal Q(t−τ) with said in-phase component I(t);
summing said bi-level operation with said complementary bi-level operation to produce a signal BB(t); and
outputting said signal BB(t), wherein said signal BB(t) has a DC voltage component substantially proportional to a frequency difference Fref−Fin, within a range of ±(1/τ).