US 6,982,572 B2 | ||
Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges, circuits and systems including same | ||
John D. Porter, Meridan, Id. (US); Dean D. Gans, Boise, Id. (US); and Larren G. Weber, Caldwell, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Jan. 03, 2003, as Appl. No. 10/336,356. | ||
Application 10/336356 is a division of application No. 09/922027, filed on Aug. 03, 2001, granted, now 6,628,139. | ||
Prior Publication US 2003/0098713 A1, May 29, 2003 | ||
Int. Cl. H03K 19/0175 (2006.01) |
U.S. Cl. 326—82 | 7 Claims |
1. A skewed buffer rising logic device for rapidly propagating a rising edge of an output signal comprising:
a fast inverter falling having a large n/p channel width ratio for receiving a rising edge of an input signal and rapidly
propagating a falling edge of an intermediate signal in response thereto;
a fast inverter rising having a large p/n channel width ratio and in series with said fast inverter falling for receiving
said rapidly propagated falling edge of said intermediate signal and rapidly propagated rising edge of said output signal;
a reset network coupled to said fast inverter falling and said fast inverter rising for resetting output signals of said fast
inverter falling and said fast inverter rising after said rising edge of said output signal has been rapidly propagated; and
a feedback delay circuit operably coupled between an output of said fast inverter rising and an input of said reset network
for propagating said output signal to said reset network.
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