US 6,983,387 B2 | ||
Microprocessor chip simultaneous switching current reduction method and apparatus | ||
David William Boerstler, Round Rock, Tex. (US); Sang Hoo Dhong, Austin, Tex. (US); Harm Peter Hofstee, Austin, Tex. (US); and Peichun Peter Liu, Austin, Tex. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Oct. 17, 2002, as Appl. No. 10/273,617. | ||
Prior Publication US 2004/0078613 A1, Apr. 22, 2004 | ||
Int. Cl. H03L 7/06 (2006.01) |
U.S. Cl. 713—322 | 18 Claims |
1. A method for reducing simultaneous switching current in a microprocessor chip, comprising:
partitioning the chip into multiple independent processor cores, each with an associated clock domain;
generating a clock signal;
independently delaying the clock signal to produce multiple independent phase-staggered clock signals, each said signal being
distributed to a differing said core and clock domain;
defining a plurality of intra-chip functions including high-speed I/O (input/output) latches and drivers associated with each
of said cores; and
distributing said intra-chip functions over the area of said chip in each of said cores clustered into areas corresponding
and proximal to each said clock domain.
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