US 6,983,339 B1 | ||
Method and apparatus for processing interrupts of a bus | ||
Jeffrey L. Rabe, Gold River, Calif. (US); Satish Acharya, El Dorado Hills, Calif. (US); Zohar Bogin, Folsom, Calif. (US); Serafin E. Garcia, Folsom, Calif. (US); and David J. Harriman, Sacramento, Calif. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Sep. 29, 2000, as Appl. No. 9/675,801. | ||
Int. Cl. G06F 1/00 (2006.01) |
U.S. Cl. 710—260 | 18 Claims |
1. A method comprising:
receiving at an IO controller hub an interrupt from an IO device;
the IO controller hub converting said interrupt into an upstream memory write interrupt by generating a memory write request
to a predetermined address of a memory space, the memory write request being processed via one or more memory cycles by a
memory controller hub; and
the memory controller hub converting said upstream memory write interrupt into a front side bus (FSB) interrupt transaction,
wherein one or more processors coupled to the FSB are capable of receiving the FSB interrupt as a part of a FSB transaction.
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