US 6,982,460 B1
Self-aligned gate MOSFET with separate gates
Guy M. Cohen, Mohegan Lake, N.Y. (US); and Hon-Sum P. Wong, Chappaqua, N.Y. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Jul. 07, 2000, as Appl. No. 9/612,260.
Int. Cl. H01L 29/76 (2006.01); H01L 27/01 (2006.01)
U.S. Cl. 257—331 37 Claims
OG exemplary drawing
 
29. A transistor comprising:
a channel region;
a first gate on top of said channel region;
a second gate below said channel region;
an isolation layer below said second gate; and
source and drain regions laterally adjacent said channel region,
wherein said source and drain regions are self-aligned with said first gate and said second gate, such that said source and drain regions do not horizontally overlap said first gate or said second gate,
wherein said first gate and said second gate are electrically separated from each other, and
wherein said first gate comprises the same material as said second gate, and has a different doping concentration than said second gate.