US 6,983,398 B2 | ||
Testing processors | ||
Manohar K. Prabhu, Palo Alto, Calif. (US) | ||
Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US) | ||
Filed on Apr. 24, 2002, as Appl. No. 10/134,343. | ||
Prior Publication US 2003/0204805 A1, Oct. 30, 2003 | ||
Int. Cl. G06F 11/00 (2006.01) |
U.S. Cl. 714—12 | 76 Claims |
1. A method for testing a chip having at least two processors, comprising the steps of:
providing a memory structure on the same chip, having various sets of data;
configuring a first processor to use a first set of data to stimulate a first portion of the chip, thereby providing a first
set of responses;
configuring a second processor to use a second set of data to stimulate a second portion of the chip, thereby providing a
second set of responses; and
configuring a processor of the at least two processors to analyze the first set of responses and/or the second set of responses.
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