1. A reconfigurable device comprising:
tiles each comprising a circuit; and
an interconnect architecture coupled to the circuit of each tile, the interconnect architecture comprising switches and registers
such that in operation at least two of the switches route a signal from a first tile to a second tile along the interconnect
architecture and further such that in operation at least two of the registers consecutively latch the signal at a time interval
of no more than a repeating time period, the repeating time period comprising a clock cycle period.
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