1. An apparatus comprising:
a sample circuit configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals
each representative of said state of said input signal during a plurality of clock cycles; and
a selection circuit configured to present a filtered signal in response to (i) a selected number of said intermediate signals
having a lost state and (ii) a multi-bit selection signal representing a filtering value, wherein said filtered signal indicates
said input signal has been lost when said selected number of lost states is greater than said filtering value.
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