US 6,982,573 B2 | ||
Switchable clock source | ||
Matt Hutson, Bristol (United Kingdom); Andrew Dellow, Minchinhampton (United Kingdom); Tom Ryan, Bristol (United Kingdom); and Paul Elliott, Bristol (United Kingdom) | ||
Assigned to STMicroelectronics Limited, Bristol (United Kingdom) | ||
Filed on Apr. 19, 2004, as Appl. No. 10/827,675. | ||
Application 10/827675 is a continuation in part of application No. 10/157731, filed on May 29, 2002, granted, now 6,774,681. | ||
Claims priority of application No. 01304738 (EP), filed on May 30, 2001. | ||
Prior Publication US 2004/0263217 A1, Dec. 30, 2004 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H03K 17/00 (2006.01) |
U.S. Cl. 327—99 | 36 Claims |
30. A clock source incorporated in a semiconductor integrated circuit for selecting a first clock signal or a second clock
signal in accordance with a switch request signal, the clock source comprising:
a first clock input for receiving the first clock signal;
a second clock input for receiving the second clock signal;
a switch request signal input for receiving the switch request signal which takes a de-asserted value when the first clock
signal is required and an asserted value when the second clock signal is required;
a retiming input signal comprising the switch request signal or a delayed version of the switch request signal;
a first retiming circuit having a first input coupled to the retiming input signal, and a second input coupled to the second
clock input, and an output at which a first retimed switch request signal is produced relative to the second clock signal;
a second retiming circuit having a first input coupled to the output of the first retiming circuit, a second input coupled
to the first clock input, and an output at which a second retimed switch request signal is produced relative to the first
clock signal;
selector circuitry coupled to the first and second retiming circuits and to the first and second clock inputs and being arranged
to switch an output of the selector circuitry to the first clock signal in response to de-assertion of the second retimed
switch request signal and to the second clock signal in response to assertion of the first retimed switch request signal;
wherein the retiming input signal has a rate of state change between the de-asserted value and the asserted value, the first
and second retiming circuits have a rate of retiming, and the rate of state change of the retiming input signal does not exceed
the rate of retiming of the first and second retiming circuits.
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