US 6,983,405 B1 | ||
Method and apparatus for testing circuitry embedded within a field programmable gate array | ||
Nigel G. Herron, San Jose, Calif. (US); Eric J. Thorne, Santa Cruz, Calif. (US); and Qingqi Wang, San Jose, Calif. (US) | ||
Assigned to Xilinx, Inc.,, San Jose, Calif. (US) | ||
Filed on Nov. 16, 2001, as Appl. No. 9/991,412. | ||
Int. Cl. G01R 31/28 (2006.01) |
U.S. Cl. 714—726 | 21 Claims |
1. A method for testing a fixed logic device formed within a gasket, comprising:
receiving an FPGA scan chain and configuring an FPGA fabric portion for a specified test;
producing a first test signal and a second test signal in the FPGA fabric portion;
providing the first test signal as input to an isolation circuit element;
providing the second test signal to a programmable interconnect resource;
selecting for input to the fixed logic device between the first signal and the second signal in response to a test mode configured
in the FPGA fabric portion;
receiving an output test signal from the fixed logic device;
applying a signature function to the received output test signal;
repeating the producing, receiving and applying steps for a specified number of times; and
determining if a value of the signature function corresponds to an expected value.
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