US 6,982,177 B2 | ||
Method for in-line testing of flip-chip semiconductor assemblies | ||
Chad A. Cobbley, Boise, Id. (US); John VanNortwick, Kuna, Id. (US); Bret K. Street, Meridian, Id. (US); and Tongbi Jiang, Boise, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Jul. 27, 2004, as Appl. No. 10/900,776. | ||
Application 10/900776 is a division of application No. 10/721110, filed on Nov. 24, 2003. | ||
Application 10/721110 is a division of application No. 10/338530, filed on Jan. 08, 2003. | ||
Application 10/338530 is a division of application No. 09/819472, filed on Mar. 28, 2001, granted, now 6,545,498, filed on Apr. 08, 2003. | ||
Application 09/819472 is a division of application No. 09/166369, filed on Oct. 05, 1998, granted, now 6,329,832, filed on Dec. 11, 2001. | ||
Prior Publication US 2004/0263197 A1, Dec. 30, 2004 | ||
Int. Cl. G01R 31/26 (2006.01) |
U.S. Cl. 438—15 | 6 Claims |
1. A method for electrically testing a flip-chip semiconductor assembly formed from at least one integrated circuit (IC) die
and a substrate, the method comprising:
inserting the substrate having pads with conductive epoxy dots thereon into a test socket;
while the substrate is in the test socket, bringing the at least one IC die and the substrate together in conductive contact
to form the flip-chip semiconductor assembly; and
before the at least one IC die is sealed, electrically testing the flip-chip semiconductor assembly using the test socket.
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