US 6,982,587 B2 | ||
Equalizing transceiver with reduced parasitic capacitance | ||
Fred F. Chen, San Francisco, Calif. (US); and Vladimir M. Stojanovic, Stanford, Calif. (US) | ||
Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
Filed on Oct. 01, 2002, as Appl. No. 10/261,875. | ||
Claims priority of provisional application 60/395283, filed on Jul. 12, 2002. | ||
Prior Publication US 2004/0008059 A1, Jan. 15, 2004 | ||
Int. Cl. G06G 7/12 (2006.01) |
U.S. Cl. 327—355 | 11 Claims |
1. A signaling circuit comprising:
a summing circuit having inputs to receive a plurality of bias values and a corresponding plurality of data values, the summing
circuit to sum the plurality of bias values according to the states of the corresponding data values to generate a summed
control value; and
an output driver circuit including a plurality of transistors, each of the transistors having a control input coupled to the
summing circuit to receive a respective bit of the summed control value, and each transistor having an output coupled to a
first output node.
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