US 6,982,464 B2 | ||
Dual silicon layer for chemical mechanical polishing planarization | ||
Krishnashree Achuthan, San Ramon, Calif. (US); Shibly S. Ahmed, San Jose, Calif. (US); Haihong Wang, Milpitas, Calif. (US); and Bin Yu, Cupertino, Calif. (US) | ||
Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
Filed on Oct. 29, 2004, as Appl. No. 10/975,473. | ||
Application 10/752691 is a division of application No. 10/459579, filed on Jun. 12, 2003, granted, now 6,756,643. | ||
Application 10/975473 is a continuation of application No. 10/752691, filed on Jan. 08, 2004, granted, now 6,812,076. | ||
Prior Publication US 2005/0056845 A1, Mar. 17, 2005 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H01L 29/72 (2006.01) |
U.S. Cl. 257—368 | 10 Claims |
1. A semiconductor device comprising:
a fin formed over an insulator, the fin including first and second ends, at least a portion of the fin acting as a substantially
vertical channel in the semiconductor device;
an amorphous silicon layer formed over at least a portion of the fin;
a polysilicon layer formed around at least the portion of the amorphous silicon layer, the amorphous silicon layer protruding
through the polysilicon layer in an area over the fin;
a source region connected to the first end of the fin; and
a drain region connected to the second end of the fin.
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