US 6,982,575 B2 | ||
Clock ratio data synchronizer | ||
Gayvin E Stong, Fort Collins, Colo. (US) | ||
Assigned to Agilent Technologies, Inc., Palo Alto, Calif. (US) | ||
Filed on Jan. 30, 2002, as Appl. No. 10/60,154. | ||
Prior Publication US 2003/0141908 A1, Jul. 31, 2003 | ||
Int. Cl. H03K 5/13 (2006.01) |
U.S. Cl. 327—141 | 17 Claims |
9. A clock ratio synchronizer for synchronizing data received by the synchronizer from a first clock domain operating at a
first clock frequency to a second clock domain operating at a second clock frequency, the first clock frequency being generated
by a first clock, the second clock frequency being generated by a second clock, the synchronizer comprising:
input logic that receives data from the first clock domain, the input logic including an input flip flop that samples data
when an edge of said first clock is received by said input flip flop, wherein when an edge of said first clock is received
by said input flip flop, said input flip flop outputs a data value corresponding to the data sampled by the input flip flop;
synchronization logic that synchronizes the data received at the input flip flop to the second clock frequency, the synchronization
logic comprising one or more synchronization flip flops and one or more multiplexers, at least one of the synchronization
flip flops sampling the data value output by said input flip flop when an edge of the second clock occurs, and wherein the
data sampled by said at least one of the synchronization flip flops is output therefrom when an edge of the second clock occurs,
and wherein each of the multiplexers receives a respective control signal that causes the respective multiplexer to output
one of two data values received thereby when the respective control signal has a certain value; and
output logic that receives data values output from said synchronization logic and outputs data therefrom at the second clock
frequency into the second clock domain, the output logic comprising at least one output flip flop that samples data on an
edge of said second clock and that outputs the data sampled by the second flip flop on an edge of said second clock.
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