US 6,982,892 B2 | ||
Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules | ||
Terry R. Lee, Boise, Id. (US); and Joseph M. Jeddeloh, Shoreview, Minn. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on May 08, 2003, as Appl. No. 10/434,578. | ||
Prior Publication US 2004/0225853 A1, Nov. 11, 2004 | ||
Int. Cl. G11C 11/401 (2006.01) |
U.S. Cl. 365—63 | 110 Claims |
1. A memory module for use in a computer system having a memory interface, comprising:
a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and
having a multi-layer structure;
at least one memory device attached to each sector of the printed circuit board, the memory devices being organized into a
plurality of memory ranks; and
at least one driver attached to the printed circuit board and operatively coupled to at least one of the memory devices from
each of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either
individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory
ranks on a particular sector may be accessed at one time, wherein the driver comprises a hub including a plurality of driver
chips.
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