US 6,983,358 B2 | ||
Method and apparatus for maintaining status coherency between queue-separated functional units | ||
Tom Elmer, Austin, Tex. (US) | ||
Assigned to IP-First, LLC, Fremont, Calif. (US) | ||
Filed on Oct. 23, 2002, as Appl. No. 10/279,213. | ||
Claims priority of provisional application 60/345456, filed on Oct. 23, 2001. | ||
Prior Publication US 2005/0273579 A1, Dec. 08, 2005 | ||
Int. Cl. G08F 9/38 (2006.01) |
U.S. Cl. 712—219 | 50 Claims |
1. An instruction queue in a microprocessor, the instruction queue comprising:
a first plurality of storage elements, each for storing an instruction to be executed by a first functional unit, said instruction
also being stored in one of a plurality of pipeline stages of a second functional unit;
a second plurality of storage elements, coupled to said first plurality of storage elements, each for storing an age of said
instruction stored in a corresponding one of said first plurality of storage elements, said age specifying which of said second
functional unit plurality of pipeline stages said instruction is stored in; and
a third plurality of storage elements, coupled to said first plurality of storage elements, each for storing a valid bit of
said instruction stored in said corresponding one of said first plurality of storage elements, said valid bit specifying whether
said instruction is valid.
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