US 6,983,357 B2 | ||
Hardware accelerator for an object-oriented programming language | ||
Thomas C. Poff, Los Altos, Calif. (US); John Shigeto Minami, San Jose, Calif. (US); and Ryo Koyama, Palo Alto, Calif. (US) | ||
Assigned to NVIDIA Corporation, Santa Clara, Calif. (US) | ||
Filed on Jun. 20, 2001, as Appl. No. 9/886,167. | ||
Application 09/886167 is a continuation of application No. 09/965540, filed on Nov. 06, 1997, granted, now 6,330,659. | ||
Claims priority of provisional application 60/045951, filed on May 08, 1997. | ||
Prior Publication US 2002/0078115 A1, Jun. 20, 2002 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. G06F 15/00 (2006.01) |
U.S. Cl. 712—34 | 32 Claims |
1. An apparatus for accelerating a processor running an object-oriented programming language, comprising:
a hardware accelerator interfaced with said processor for implementing at least one application framework of said object-oriented
programming language, wherein said at least one application framework comprises a set of classes that embodies an abstract
design for solutions to a number of related problems; and
a software stub that controls interfacing of said hardware accelerator with said processor;
wherein said hardware accelerator comprises:
an Input/Output request queue interacting with said processor for receiving and sequentially storing said instructions pending
execution of each instruction;
a task processor for processing said instructions from said Input/Output request queue; and
an active object list for tracking the number of reference counts to an instance and for deallocating an instance that is
not in use based upon a result of said task processor processing said instructions.
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