US 6,982,471 B2
Semiconductor memory device
Kang Seol Lee, Seoul (Korea, Republic of); and Ji Hoon Lee, Gyeonggi-do (Korea, Republic of)
Assigned to Hynix Semiconductor Inc., Gyeonggi-do (Kuwait)
Filed on Dec. 18, 2003, as Appl. No. 10/738,086.
Claims priority of application No. 10-2003-0033158 (KR), filed on May 24, 2003.
Prior Publication US 2004/0232518 A1, Nov. 25, 2004
Int. Cl. H01L 29/00 (2006.01)
U.S. Cl. 257—529 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device including a fuse box comprising:
a plurality of cell matrices arranged adjacently to each other;
a fuse box defined by a fuse barrier layer formed at a side of the plurality of cell matrices, wherein the fuse box comprises a plurality of fuses shared by the plurality of cell matrices and, divided into a plurality of blocks, the fuse barrier layer is configured to have a length long enough to be shared by the plurality of cell matrices; and
an index mark corresponding to each of the plurality of blocks is formed adjacent to the fuse box.