US 6,982,576 B2
Signal delay compensating circuit
Masahiro Ito, Iwata (Japan)
Assigned to Yamaha Corporation, Hamamatsu (Japan)
Filed on Oct. 10, 2003, as Appl. No. 10/684,187.
Claims priority of application No. P. 2002-298597 (JP), filed on Oct. 11, 2002.
Prior Publication US 2004/0124895 A1, Jul. 01, 2004
Int. Cl. H03L 7/00 (2006.01)
U.S. Cl. 327—141 4 Claims
OG exemplary drawing
 
1. A digital signal delay compensating circuit:
a first semiconductor circuit device including a clock-signal generating circuit and a data processing circuit for outputting a data signal in synchronism with a clock signal generated by the clock-signal generating circuit; and
a second semiconductor circuit device to which the data signal output from the first semiconductor circuit device is inputted and which processes the data signal in synchronism with the clock signal,
wherein the clock signal to be supplied from the first semiconductor circuit device to the second semiconductor circuit device is fed back to the data processing circuit, and the fed-back clock signal is used as a clock signal at the time of outputting the data signal.