US 6,982,556 B2
System and method for classifying defects in and identifying process problems for an electrical circuit
Kyo Young Chung, San Jose, Calif. (US)
Assigned to YieldBoost Tech, Inc., San Jose, Calif. (US)
Filed on Aug. 25, 2003, as Appl. No. 10/646,688.
Application 10/646688 is a continuation in part of application No. 10/455359, filed on Jun. 06, 2003.
Prior Publication US 2005/0001646 A1, Jan. 06, 2005
Int. Cl. G01R 31/08 (2006.01)
U.S. Cl. 324—527 45 Claims
OG exemplary drawing
 
1. A method for performing defect analysis, comprising:
applying a test signal to a circuit;
obtaining a signal generated in response to the test signal;
comparing the response signal to reference information;
classifying a defect in the circuit based on a result of the comparing step; and
identifying a problem in a manufacturing process which caused the defect based on said defect classification, wherein the problem in the manufacturing process is identified by;
comparing the defect classification to statistical information which links a plurality of predefined defect classifications to a plurality of corresponding manufacturing process problems.