US 6,983,228 B2 | ||
Graphical program having a timing specification and method for conversion into a hardware implementation | ||
Jeffrey L. Kodosky, Austin, Tex. (US); Hugo Andrade, Austin, Tex. (US); Brian K. Odom, Pflugerville, Tex. (US); and Cary P. Butler, Austin, Tex. (US) | ||
Assigned to National Instruments Corporation, Austin, Tex. (US) | ||
Filed on May 09, 2003, as Appl. No. 10/434,950. | ||
Application 10/434950 is a continuation of application No. 09/788104, filed on Feb. 16, 2001. | ||
Application 09/788104 is a continuation of application No. 08/912427, filed on Aug. 18, 1997, granted, now 6,219,628, filed on Apr. 17, 2001. | ||
Prior Publication US 2003/0195730 A1, Oct. 16, 2003 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. G06F 7/60 (2006.01) |
U.S. Cl. 703—2 | 32 Claims |
1. A memory medium which stores program instructions for configuring a device, wherein the device includes a programmable
hardware element, wherein the program instructions are executable by a processor to perform:
storing a block diagram, wherein the block diagram specifies a function, wherein the block diagram comprises a timing specification
visually depicted in the block diagram specifying timing information of the block diagram;
generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation
of the block diagram, wherein the hardware description incorporates the timing specification; and
configuring the programmable hardware element in the device utilizing the hardware description to produce a configured hardware
element, wherein the configured hardware element implements a hardware implementation of the block diagram, wherein the configured
hardware element is operable to perform the function according to the timing specification.
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