US 6,982,602 B2
Low voltage input current mirror circuit and method
Lawrence M. Burns, Laguna Hills, Calif. (US)
Assigned to Broadcom Corporation, Irvine, Calif. (US)
Filed on Oct. 07, 2003, as Appl. No. 10/679,269.
Application 10/679269 is a continuation of application No. 10/288418, filed on Nov. 06, 2002, granted, now 6,714,080.
Application 10/288418 is a continuation of application No. 09/897045, filed on Jul. 03, 2001, granted, now 6,531,923.
Claims priority of provisional application 60/221835, filed on Jul. 28, 2000.
Claims priority of provisional application 60/215850, filed on Jul. 03, 2000.
Prior Publication US 2004/0066235 A1, Apr. 08, 2004
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 3/04 (2006.01)
U.S. Cl. 330—296 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate; and
a bias circuit, disposed on the substrate, for establishing a plurality of bias voltages from an input current supplied to an input terminal, the bias circuit comprising
an input stage adapted to establish a first bias voltage at the input terminal in response to the input current,
a current stage adapted to produce a bias current and a main mirror current each proportional to the input current in response to the first bias voltage and a second bias voltage,
a feedback stage adapted to produce a feedback current proportional to the input current in response to the bias current and the main mirror current, and
a reference bias stage adapted to establish the second bias voltage in response to the feedback current from the feedback stage, whereby the first and second bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.