US 6,982,895 B2
Method for reading a passive matrix-addressable device and a device for performing the method
Per Bröms, Linkoping (Sweden); and Christer Karlsson, Linkoping (Sweden)
Assigned to Thin Film Electronics ASA, Oslo (Norway)
Filed on Nov. 07, 2002, as Appl. No. 10/289,419.
Claims priority of application No. 2001 5879 (NO), filed on Nov. 30, 2001.
Prior Publication US 2003/0103386 A1, Jun. 05, 2003
Int. Cl. G11C 11/22 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01); G11C 8/18 (2006.01)
U.S. Cl. 365—145 20 Claims
OG exemplary drawing
 
1. A method for reading a passive matrix-addressable device with individually addressable cells for storing a logical value as given by charge value set in a cell, wherein the device comprises electrically polarizable material exhibiting hysteresis, wherein the device comprises a first and a second electrode set with parallel electrodes which respectively form word lines and bit lines in the device, wherein the word line electrodes and the bit line electrodes are provided mutually orthogonal and contacting the polarizable material at opposite surfaces thereof, such that the cells of the device comprise capacitor-like structures defined in a volume of the polarizable material in or at the crossings between word lines and bit lines, wherein the cell in the device can be set to one of two polarization states or switched between these by applying a voltage Vs larger than the coercive voltage Vc of the polarizable material between a word line and a bit line addressing the cell, wherein each bit line is connected with detection means, wherein the method comprises a voltage pulse protocol with a read cycle such that each detection means during the read cycle detects charges flowing between its associated bit line and cells connected with this bit line, and wherein the method includes:
activating an active word line at least during a part of the read cycle by an applied potential which relative to the potential of all crossing bit lines at least corresponds to the voltage Vs;
enabling a parallel readout of the logical values stored in all individual cells connected with the active word line by detecting the charge values in the detection means; and
controlling simultaneously electric potentials on all word and bit lines in a time-coordinated manner according to the voltage pulse protocol, said voltage pulse protocol comprising timing sequences for the electric potentials on all word and bit lines.