US 6,983,406 B2 | ||
Method and system for partial-scan testing of integrated circuits | ||
A. Kent Porterfield, New Brighton, Minn. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Aug. 21, 2002, as Appl. No. 10/225,015. | ||
Application 10/225015 is a division of application No. 09/651456, filed on Aug. 30, 2000, granted, now 6,515,483. | ||
Prior Publication US 2002/0194562 A1, Dec. 19, 2002 | ||
Int. Cl. G01R 31/28 (2006.01) |
U.S. Cl. 714—726 | 28 Claims |
9. An integrated circuit, comprising:
a plurality of functional blocks; and
logical circuitry connected to at least one of the functional blocks to selectively isolate one or more failed functional
blocks from one or more non-failed functional blocks by routing at least one output from at least one of the non-failed functional
blocks to at least one input of that non-failed functional block.
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