US 6,982,197 B2
Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
Joseph W. Ku, Palo Alto, Calif. (US); and Paul Vande Voorde, San Mateo, Calif. (US)
Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US)
Filed on Feb. 07, 2002, as Appl. No. 10/67,317.
Prior Publication US 2003/0148578 A1, Aug. 07, 2003
Int. Cl. H01L 21/8242 (2006.01); H01L 21/20 (2006.01)
U.S. Cl. 438—239 19 Claims
OG exemplary drawing
 
15. An integrated circuit comprising:
a circuit function block having a predetermined circuit layout; and
an inter-digitated capacitance structure comprising at least one metal plate and a plurality of inter-digitated metal fingers on top of the circuit function block, wherein a plurality of de-coupling capacitances are formed between the inter-digitated capacitance structure, a first metal layer, and a second metal layer.