US 6,982,227 B2 | ||
Single and multilevel rework | ||
Edward C. Cooney, III, Jericho, Vt. (US); Robert M. Geffken, Burlington, Vt. (US); Vincent J. McGahay, Poughkeepsie, N.Y. (US); William T. Motsiff, Essex Junction, Vt. (US); Mark P. Murray, Burlington, Vt. (US); Amanda L. Piper, Wappingers Falls, N.Y. (US); Anthony K. Stamper, Williston, Vt. (US); David C. Thomas, Richmond, Vt. (US); Christy S. Tyberg, East Mohopac, N.Y. (US); and Elizabeth T. Webster, Richmond, Vt. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Oct. 16, 2003, as Appl. No. 10/687,294. | ||
Application 10/687294 is a division of application No. 10/248452, filed on Jan. 21, 2003, granted, now 6,674,168. | ||
Prior Publication US 2004/0142565 A1, Jul. 22, 2004 | ||
Int. Cl. H01L 21/302 (2006.01) |
U.S. Cl. 438—706 | 6 Claims |
1. A method of reworking interconnection layers above logical and functional layers of an integrated circuit structure, wherein
said interconnection layers comprise an upper insulator layer above a lower insulator layer and electrical wiring, wherein
said lower insulator layer has a lower dielectric constant than that of said upper insulator layer, said method comprising:
removing a first upper insulator of a first interconnection layer of said interconnection layers; and
removing a first electrical wiring and a first lower insulator of said first interconnection layer in a selective removal
process that does not affect a second upper insulator of a second interconnect layer positioned immediately below said first
interconnect layer.
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