US 6,982,581 B2
Duty cycle correction circuit
Shiro Dosho, Osaka (Japan); Naoshi Yanagisawa, Osaka (Japan); Masaomi Toyama, Osaka (Japan); and Keijiro Umehara, Kyoto (Japan)
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan)
Filed on Nov. 17, 2003, as Appl. No. 10/713,162.
Claims priority of application No. 2002-354732 (JP), filed on Dec. 06, 2002.
Prior Publication US 2004/0108878 A1, Jun. 10, 2004
Int. Cl. H03K 3/017 (2006.01)
U.S. Cl. 327—175 3 Claims
OG exemplary drawing
 
1. A 50% duty cycle clock-signal production circuit comprising:
a delay unit for receiving a first clock signal in which a first logic value has a shorter period of time per cycle than a second logic value, delaying the first clock signal and outputting a second clock signal which transitions to the second logic value at a timing at which the period of time equivalent to a half cycle has elapsed since the first clock signal transitioned to the first logic value;
a clock-signal output unit for outputting a third clock signal based on the first and second clock signals; and
a frequency divider circuit for producing the first clock signal,
wherein the clock-signal output unit comprises:
a first output unit for setting the third clock signal at a first logic output value with either one of the first logic value and the second logic value in response to the transition of the first clock signal to the first logic value; and
a second output unit for setting the third clock signal at a second logic output value with the other of the first logic value and the second logic value in response to the transition of the second clock signal to the second logic value;
wherein the delay unit includes a transistor whose gate is supplied with a predetermined voltage and of which either one of a source and a drain receives the first clock signal to output the second clock signal from the other of the drain and the source,
the predetermined voltage supplied to the gate of the transistor is above a gate threshold value in the case where the transistor is an n-channel transistor while the predetermined voltage supplied to the gate of the transistor is below the gate threshold value in the case where the transistor is a p-channel transistor,
the frequency divider circuit is formed of at least one n-channel transistor and at least one p-channel transistor,
the clock-signal output unit is formed of at least one n-channel transistor and at least one p-channel transistor, and
the numbers of n-channel and p-channel transistors through which a signal travels in the rising of the third clock signal are equal to those through which a signal travels in the falling of the third clock signal.