US 6,982,591 B2 | ||
Method and circuit for compensating for tunneling current | ||
Wagdi W. Abadeer, Jericho, Vt. (US); Jennifer E. Appleyard, Burlington, Vt. (US); John A. Fifield, Underhill, Vt. (US); and William R. Tonti, Essex Junction, Vt. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Dec. 09, 2003, as Appl. No. 10/731,298. | ||
Prior Publication US 2005/0122160 A1, Jun. 09, 2005 | ||
Int. Cl. G05F 1/10 (2006.01); G05F 3/02 (2006.01) |
U.S. Cl. 327—543 | 17 Claims |
1. A circuit comprising:
a tunneling leakage monitor circuit, said tunneling leakage monitor circuit comprising a first PFET, a second PFET, a first
NFET and a second NFET, sources of said first and second PFETS connected to a voltage source, gates of said first and second
PFETs and said drain of said first PFET connected to a drain of said first NFET, a drain of said second PFET connected to
a gate of said second NFET, sources of said first and second NFETs and a drain of said second NFET connected to ground;
a current mirror connected to a gate of said first NFET, said current mirror adapted to force a current of a predetermined
value from said gate of said second NFET, through a gate dielectric layer of said second NFET, through said source and said
drain of said second NFET to ground, said current consisting of tunneling leakage current;
an input of a voltage buffer connected to said gate of said second NFET, said voltage buffer adapted to generate an output
voltage based on a voltage level developed across said gate dielectric layer of said second NFET when said current is at said
predetermined current value; and
a voltage regulator coupled to said voltage burner, said voltage regulator adapted to supply a fixed voltage to a power distribution
network of an integrated circuit chip based on said output voltage of said voltage buffer.
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