US 6,982,912 B2
Semiconductor memory device
Yoshinobu Yamagami, Nagaokakyo (Japan)
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan)
Filed on Apr. 28, 2004, as Appl. No. 10/833,922.
Claims priority of application No. 2003-164165 (JP), filed on Jun. 09, 2003.
Prior Publication US 2004/0246793 A1, Dec. 09, 2004
Int. Cl. G11C 29/00 (2006.01)
U.S. Cl. 365—200 9 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of word lines including one or more redundant word lines;
a plurality of pairs of bit lines;
a plurality of memory cells connected to said plurality of word lines and said plurality of pairs of bit lines;
a plurality of word-line drivers, each of which is connected to one end of each of said plurality of word lines and controlled by a plurality of word-line control signals; and
a plurality of first word-line control circuits respectively located at the other ends of said plurality of word lines, each of said plurality of first word-line control circuits receiving a signal level of a corresponding one of said plurality of word lines, wherein
in the case where the signal level of said corresponding word line is a first level at which corresponding ones of said plurality of memory cells connected to said corresponding word line go into a high impedance state, each of said plurality of first word-line control circuits switches to a conducting state and outputs a signal of said first level to said corresponding word line, and
in the case where the signal level of said corresponding word line is a second level at which said corresponding memory cells go into a state wherein data input/output is performed, each of said plurality of first word-line control circuits switches to a non-conducting state.