US 6,983,359 B2
Processor and method for pre-fetching out-of-order instructions
William V. Miller, Arlington, Tex. (US)
Assigned to VIA-Cyrix, Inc., Fremont, Calif. (US)
Filed on Aug. 13, 2003, as Appl. No. 10/640,592.
Prior Publication US 2005/0038976 A1, Feb. 17, 2005
Int. Cl. G06F 9/38 (2006.01)
U.S. Cl. 712—228 17 Claims
OG exemplary drawing
 
1. A processor comprising:
memory access logic configured to generate a signal indicative of an active memory access;
instruction pre-fetch logic configured to pre-fetch instructions from memory;
instruction information logic configured to store information about instructions fetched from memory; and
control logic configured to control temporary storage of the information related to a pre-fetched instruction if there is currently an active memory access and the currently pre-fetched instruction is an out-of-order instruction.