US 6,983,346 B2
Reducing tag-ram accesses and accelerating cache operation during cache miss
Jonathan Y. Zhang, Plano, Tex. (US)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on May 09, 2003, as Appl. No. 10/435,357.
Claims priority of provisional application 60/379503, filed on May 10, 2002.
Prior Publication US 2004/0024967 A1, Feb. 05, 2004
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—138 2 Claims
OG exemplary drawing
 
2. An apparatus performing cache memory control comprised of:
a last miss-address register storing a last miss-line address of a last received memory access request address which generated a cache miss, said last miss-address register being initialized with said current access request address upon a cache miss;
a miss-line valid indicator set to valid upon initialization of said last miss-address register and reset to invalid upon a cache fill operation of data corresponding to said last miss-line address;
a last hit-address register storing a last hit-line address of a last received memory access request address which generated a cache hit, said last hit-address register is initialized with said current access request address upon a cache hit;
a hit-line valid indicator set to valid upon initialization of said last hit-address register and reset to invalid upon cache line replacement corresponding to said last hit-line address;
a cache line comparator comparing a current memory access request address to both said last miss-line address stored in said last miss-address register and said last hit-line address stored in said last hit-address register, said cache line comparator providing a match indication
if said current memory access address matches said last miss-line address and said miss-line valid indicator indicates valid, or
if said current memory access address matches said last hit-line address and said hit-line valid indicator indicates valid; and
providing a non-match indication
if said current memory access address matches neither said last miss-line address nor said last hit-line address,
if said current memory access address matches said last miss-line address and said last miss-line valid indicator indicates invalid, or
if said current memory access address matches said last hit-line address and the last hit-address valid indicator indicates invalid;
a cache data-RAM storing data and corresponding memory addesses;
a tag-RAM storing indications of addresses of data stored in cache data-RAM;
a tag-RAM controller connected to said cache line comparator and said tag-RAM, said tag-RAM controller operative to
prohibit access to said tag-RAM to determine if data corresponding to said current memory access request address is stored in said cache data-RAM if said cache line comparator provides said match indication, and
enable access to said tag-RAM to determine if data corresponding to said current memory access request address is stored in said cache data RAM if said cache line comparator provides said non-match indication.