US 6,982,222 B2 | ||
Method of generating interconnection pattern | ||
Chiaki Kudo, Amagasaki (Japan) | ||
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan) | ||
Filed on Aug. 24, 2004, as Appl. No. 10/923,869. | ||
Claims priority of application No. 2003-299464 (JP), filed on Aug. 25, 2003. | ||
Prior Publication US 2005/0048764 A1, Mar. 03, 2005 | ||
Int. Cl. H01L 21/4763 (2006.01) |
U.S. Cl. 438—622 | 2 Claims |
1. An interconnection pattern generation method of generating an interconnection pattern for a mask layout corresponding to
an interconnection which connects between a plurality of elements based on circuit data, comprising the steps of:
generating a first interconnection pattern corresponding to said interconnection with a line width according to minimum line
width data and an interconnection spacing determined from said minimum line width;
generating a second interconnection pattern corresponding to said interconnection with a line spacing according to a minimum
line spacing data and a line width determined from said minimum line spacing; and
generating a third interconnection pattern corresponding to said interconnection with a medium line width and a medium line
spacing of said first and second interconnection patterns based on said first and second interconnection patterns to use said
third interconnection pattern as said interconnection pattern for a mask layout.
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