US 6,982,988 B2
Programmable frame splitter
Michael E Rupp, Amherst, N.Y. (US); Ronald D Olsen, Lake View, N.Y. (US); and Jon C Melnik, Alden, N.Y. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Jan. 10, 2002, as Appl. No. 10/44,766.
Prior Publication US 2003/0128721 A1, Jul. 10, 2003
Int. Cl. H04J 3/16 (2006.01)
U.S. Cl. 370—470 27 Claims
OG exemplary drawing
 
1. A programmable frame splitter, comprising:
a plurality of programmable routers connected to a communication line, each of said routers having logic to control loading and startup of said routers, and logic to specify which bits of a frame of serial data is passed to an output of each of said routers; and
a plurality of field processing units to receive a bit clock out signal from each of said routers and serial data from the communication line, wherein each of said field processing units splits the frame of serial data into component fields and performs processing on the component fields wherein a control unit receives a bus signal, a frame start signal, and a bit-clock-in signal.