US 6,982,203 B2 | ||
Method of fabricating integrated circuitry | ||
H. Montgomery Manning, Eagle, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Dec. 05, 2003, as Appl. No. 10/729,260. | ||
Application 10/729260 is a division of application No. 10/418540, filed on Apr. 17, 2003, granted, now 6,803,286. | ||
Application 10/087147 is a division of application No. 09/608333, filed on Jun. 29, 2000, granted, now 6,391,726. | ||
Application 09/608333 is a division of application No. 09/266456, filed on Mar. 11, 1999, granted, now 6,180,494. | ||
Application 10/418540 is a continuation of application No. 10/087147, filed on Feb. 28, 2002, granted, now 6,638,842. | ||
Prior Publication US 2004/0115914 A1, Jun. 17, 2004 | ||
Int. Cl. H01L 21/336 (2006.01) |
U.S. Cl. 438—265 | 31 Claims |
1. A method of fabricating integrated circuitry comprising:
forming a conductive line having opposing sidewalls over a semiconductor substrate, the conductive line having an outer etch
stop cap;
depositing an insulating layer over the substrate and the line;
planarize polishing the insulating layer using the outer etch stop cap as an etch stop;
after the planarize polishing, etching the insulating layer proximate the line along at least a portion of at least one sidewall
of the line; and
after the etching, depositing an insulating spacer forming layer over the substrate and the line, and anisotropically etching
it to form an insulating sidewall spacer along said portion of the at least one sidewall.
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