US 6,983,414 B1
Error insertion circuit for SONET forward error correction
Douglas E. Duschatko, McKinney, Tex. (US); and Andrew J. Thurston, Allen, Tex. (US)
Assigned to Cisco Technology, Inc., San Jose, Calif. (US)
Filed on Mar. 30, 2001, as Appl. No. 9/821,948.
Int. Cl. H03M 13/00 (2006.01)
U.S. Cl. 714—782 39 Claims
OG exemplary drawing
 
1. A method of verifying correct operation of a forward error correction decoder, comprising the steps of:
programmably selecting a desired number of errors for insertion into a plurality of data signals;
defining a plurality of code words of the data signals;
inserting into one of the data signals the desired number of errors using an error insertion circuit;
repeating said inserting step in an iterative fashion to insert into different data signals the desired number of errors wherein the errors are placed within the code words of the data signals at different location permutations for each data signal;
transmitting the data signals with the inserted errors to a receiver; and
determining that the data signals received at the receiver contain the inserted errors.