US 6,983,348 B2 | ||
Methods and apparatus for cache intervention | ||
Sujat Jamil, Chandler, Ariz. (US); Hang Nguyen, Tempe, Ariz. (US); Samantha J. Edirisooriya, Tempe, Ariz. (US); David E. Miner, Chandler, Ariz. (US); R. Frank O'Bleness, Tempe, Ariz. (US); and Steven J. Tu, Phoenix, Ariz. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Nov. 25, 2002, as Appl. No. 10/303,931. | ||
Application 10/303931 is a continuation in part of application No. 10/073492, filed on Feb. 11, 2002. | ||
Application 10/073492 is a continuation in part of application No. 10/057493, filed on Jan. 24, 2002, granted, now 6,775,748. | ||
Prior Publication US 2003/0154352 A1, Aug. 14, 2003 | ||
Int. Cl. G06F 12/00 (2006.01) |
U.S. Cl. 711—146 | 24 Claims |
1. A method comprising:
snooping a cache interconnect to detect a memory read request associated with a cached memory block cached in a first cache
and cached in a second cache;
asserting a first signal line indicative of a cache hit in response to snooping the cache interconnect if the cached memory
block is in the first cache in an unmodified state;
asserting a second signal line indicative of a cache hit in response to snooping the cache interconnect if the cached memory
block is in the second cache in an unmodified state; and
upon a cache hit to the first and second caches, supplying the cached memory block from the first cache or the second cache
to a third cache based on a predetermined arbitration hierarchy, wherein the first cache, the second cache, and the cache
interconnect are located in a single device and the single device is a multi-processor system.
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