US 6,982,202 B2
Fabrication method for memory cell
Franz Hofmann, Munich (Germany); Erhard Landgraf, Munich (Germany); and Hannes Luyken, Munich (Germany)
Assigned to Infineon Technologies AG, Munich (Germany)
Filed on Jul. 26, 2004, as Appl. No. 10/899,436.
Application 10/899436 is a continuation of application No. PCT/DE03/00183, filed on Jan. 23, 2003.
Claims priority of application No. 102 04 873 (DE), filed on Feb. 06, 2002.
Prior Publication US 2005/0032311 A1, Feb. 10, 2005
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—259 6 Claims
OG exemplary drawing
 
1. A method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions, comprising the steps of:
fabricating at least one trench in the top side;
providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer;
depositing a material provided for the gate electrode into the trench;
forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant; and
applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.