US 6,982,924 B2 | ||
Data output control circuit | ||
Kwang-Jin Na, Ichon-shi (Korea, Republic of) | ||
Assigned to Hynix Semiconductor Inc., Ichon-shi (Korea, Republic of) | ||
Filed on Jun. 25, 2004, as Appl. No. 10/875,387. | ||
Claims priority of application No. 10-2003-0076835 (KR), filed on Oct. 31, 2003. | ||
Prior Publication US 2005/0094443 A1, May 05, 2005 | ||
Int. Cl. G11C 8/00 (2006.01) |
U.S. Cl. 365—233 | 7 Claims |
1. A data output control circuit for use in a semiconductor memory device, comprising:
a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enable
signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency; and
a second data output enable signal generation unit for receiving the rising data output enable signal and generating a falling
data output enable signal synchronizing with a falling edge of the DLL clock signal.
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