US 6,982,899 B2
Semiconductor memory device
Norihiko Sumitani, Osaka (Japan); Shigeo Houmura, Kyoto (Japan); Youji Nakai, Osaka (Japan); Hidenari Kanehara, Osaka (Japan); and Kazuki Tsujimura, Shiga (Japan)
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan)
Filed on Jan. 08, 2004, as Appl. No. 10/752,663.
Claims priority of application No. 2003-004036 (JP), filed on Jan. 10, 2003.
Prior Publication US 2004/0141362 A1, Jul. 22, 2004
Int. Cl. G11C 11/00 (2006.01)
U.S. Cl. 365—154 8 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a six-transistor memory cell; and
a word line and a pair of bit lines, the word line and the pair of bit lines being connected to the memory cell,
the semiconductor memory device further comprising:
means for precharging the pair of bit lines to a power source voltage;
a dummy bit line different from the pair of bit lines;
means for discharging the dummy bit line to a first voltage lower than the power supply voltage; and
means for equalizing the pair of bit lines precharged to the power source voltage and the dummy bit line discharged to the first voltage to set the voltages on the pair of bit lines before read operation of the memory cell at a second voltage lower than the power supply voltage.