US 6,982,909 B2
System and method for reading a memory cell
Frederick A. Perner, Palo Alt, Calif. (US); Kenneth K. Smith, Boise, Id. (US); and Corbin L. Champion, Pullman, Wash. (US)
Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US)
Filed on Jan. 27, 2004, as Appl. No. 10/765,483.
Application 10/765483 is a continuation in part of application No. 10/614504, filed on Jul. 07, 2003, granted, now 6,836,422.
Prior Publication US 2005/0007830 A1, Jan. 13, 2005
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01)
U.S. Cl. 365—189.07 15 Claims
OG exemplary drawing
 
1. A system comprising:
a memory cell string that includes a first memory cell coupled to a second memory cell;
a sense amplifier coupled to the memory cell string and configured to:
detect a first voltage at a node between the first and second memory cells at a first time;
detect a second voltage at the node at a second time subsequent to a write sense current being applied across the first memory cell;
compare the first and second voltages; and
cause a logic level associated with the first memory cell to be stored in response to comparing the first and second voltages.