US 6,982,942 B2 | ||
Data recording and/or reproducing apparatus for demodulating data from a reproduction signal | ||
Akiyoshi Uchida, Kawasaki (Japan); and Masakazu Taguchi, Kawasaki (Japan) | ||
Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
Filed on Mar. 12, 2002, as Appl. No. 10/96,280. | ||
Claims priority of application No. 2001-317039 (JP), filed on Oct. 15, 2001. | ||
Prior Publication US 2003/0072242 A1, Apr. 17, 2003 | ||
Int. Cl. G11B 7/005 (2006.01) |
U.S. Cl. 369—59.22 | 9 Claims |
9. A data recording/reproducing apparatus comprising:
a write unit for writing data obtained by modulating original data in accordance with a predetermined run length limitation
to a recording medium; and
a read unit for reproducing data from a reproduction signal in accordance with a partial response waveform obtained from the
recording medium by a Viterbi decoding technique based on front edge sampling values obtained by sampling while synchronizing
a front edge clock synchronizing a leading edge of the reproduction signal and back edge sampling values obtained by sampling
while synchronizing a back edge clock synchronizing a trailing edge of the reproduction signal,
wherein:
said write unit comprises:
a parity bit determining part determining values of parity bits to be additionally provided every one predetermined length
block in data obtained by modulating said original data, so as to satisfy a part of or an entire said predetermined run length
limitation rule in ranges of a current predetermined length block in which said plurality of parity bits are additionally
provided, said plurality of parity bits, and a next predetermined length block that is positioned next to said current predetermined
length block; and
a parity adding part adding said parity bits having said values determined by said parity bit determining part to said current
predetermined length block,
wherein data, in which said parity bits are provided every one predetermined length block, are written in said recording medium,
said read unit comprises:
a front edge system processing said front edge sampling values;
a back edge system processing said back edge sampling values; and
a processing system modulating data based on information obtained individually from said front edge system and said back edge
system,
wherein:
said front edge system comprises:
a first selection path selecting part selecting one path as a first selection path so as to correspond to a state transition
of data according to a predetermined rule that is based on results from calculating a branch metric value using each expected
value defined by said partial response waveform and each of said front edge sampling values, calculating a path metric value
based on every said branch metric value, and comparing among a plurality of said path metric values;
a first generating part generating front edge candidate data corresponding to said first selection path selected by said first
selection path selecting part; and
a first change path selecting part selecting one path different from said first selection path as a first change path based
on differences among the plurality of said path metric values to be compared by said first selection path selecting part,
said back edge system comprises:
a second selection path selecting part selecting one path as a second selection path so as to correspond to the state transition
of data according to the predetermined rule that is based on results from calculating a branch metric value using each expected
value defined by said partial response waveform and each of said back edge sampling values, calculating a path metric value
based on every said branch metric value, and comparing among a plurality of said branch metric values;
a second generating selecting part generating back edge candidate data corresponding to said second selection path selected
by said second selection path selecting part; and
a second change path selecting part selecting one path different from said second selection path as a second change path based
on differences among the plurality of said path metric values to be compared by said second selection path selecting part,
and
said processing system comprises:
a first candidate data generating part generating first candidate data by synthesizing said front edge candidate data from
said front edge system with said back edge candidate data from said back edge system;
a mixed selection path generating part generating a mixed selection path based on said first selection path from said front
edge system and said second selection path from said back edge system;
a second candidate data generating part changing paths that are of said mixed selection path and correspond to said first
change path from said front edge system and said second change path from said back edge system, to said change paths as change
selection paths, and generating second candidate data in accordance with said Viterbi decoding technique based on said change
selection paths;
a data selecting part selecting either of said first candidate data and said second candidate data based on error detection
result in accordance with an addition rule of said parity bits with respect to said first candidate data and said second candidate
data;
a parity deleting part deleting parity bits additionally provided in accordance with said predetermined addition rule from
said first candidate data and said second candidate data that are selected by said data selecting part; and
a data demodulating part demodulating remaining data parts in which said parity bits are deleted from said first candidate
data and said second candidate data that are selected by said data selecting part.
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