US 6,983,235 B2
Method and apparatus for implementing constant latency Z-domain transfer functions using processor elements of variable latency
David Stark, San Jose, Calif. (US)
Assigned to Juniper Networks, Inc., Sunnyvale, Calif. (US)
Filed on Apr. 24, 2001, as Appl. No. 9/841,031.
Claims priority of provisional application 60/199899, filed on Apr. 26, 2000.
Prior Publication US 2002/0010897 A1, Jan. 24, 2002
Int. Cl. G06F 17/50 (2006.01); H04M 1/64 (2006.01)
U.S. Cl. 703—19 31 Claims
OG exemplary drawing
 
1. A method of designing digital signal processing hardware to implement a z-domain transfer function, wherein the processing of signal samples is characterized by constant latency, the method comprising:
a) specifying said transfer function;
b) without regard to latency characteristics, specifying a first hardware stage to process said signal samples in accordance with said transfer function; and
c) specifying a second hardware stage to dynamically and selectively delay said signal samples processed by said first hardware stage such that the combined first and second stage latency for the processing of said signal samples is a constant.