US 6,982,487 B2
Wafer level package and multi-package stack
Hyeong-Seob Kim, Cheonan (Korea, Republic of); and Tae-Gyeong Chung, Suwon (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (Korea, Republic of)
Filed on Sep. 22, 2003, as Appl. No. 10/665,630.
Claims priority of application No. 10-2003-0018446 (KR), filed on Mar. 25, 2003.
Prior Publication US 2004/0188837 A1, Sep. 30, 2004
Int. Cl. H01L 23/48 (2006.01)
U.S. Cl. 257—774 35 Claims
OG exemplary drawing
 
1. A semiconductor chip package, comprising:
a semiconductor chip which includes a through hole extending there through from an active first surface to an inactive second surface;
a first conductive pad which at least partially surrounds the through hole on the active first surface of the semiconductor chip;
a printed circuit board which includes a first surface attached to the inactive second surface of the semiconductor chip, and which further includes a second conductive pad aligned with the through hole of the semiconductor chip; and
a conductive material which fills the through hole and directly contacts the first and second conductive pads.