US 6,983,342 B2
High speed OC-768 configurable link layer chip
Victor Helenic, Shrewsbury, Mass. (US); Clinton P. Seeman, Blackstone, Mass. (US); and Danny C. Vogel, Sudbury, Mass. (US)
Assigned to LSI Logic Corporation, Milpitas, Calif. (US)
Filed on Oct. 08, 2002, as Appl. No. 10/266,232.
Prior Publication US 2004/0068593 A1, Apr. 08, 2004
Int. Cl. G06F 13/14 (2006.01); H04Q 11/00 (2006.01)
U.S. Cl. 710—305 21 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an interface controller configured to implement one or more communication protocols;
a plurality of first link layer controllers coupled to said interface controllers;
a plurality of first serializer/deserializer (SERDES) circuits; and
a plurality of first customizable logic circuits each coupling one of said plurality of link layer controllers with one of said plurality of serializer/deserializer circuits, wherein said integrated circuit is implemented as a single chip and said plurality of link layer controllers operate independently to provide a plurality of low-speed communication channels in a first mode and cooperatively to provide a single high-speed communication channel in a second mode.