US 6,982,920 B2
Flash array implementation with local and global bit lines
Christophe Chevallier, Palo Alto, Calif. (US)
Assigned to Micron Technology, Inc., Boise, Id. (US)
Filed on Feb. 23, 2004, as Appl. No. 10/784,442.
Application 10/784442 is a division of application No. 10/017664, filed on Dec. 12, 2001, granted, now 6,795,326.
Prior Publication US 2004/0165437 A1, Aug. 26, 2004
Int. Cl. G11C 11/00 (2006.01)
U.S. Cl. 365—230.02 22 Claims
OG exemplary drawing
 
1. A flash memory system comprising:
an array of flash memory cells;
four local bit lines positioned generally parallel with each other;
a first and a second global bit line;
a first multiplex circuit to selectively couple a first pair of the four local bit lines with the first global bit line, wherein the first pair of local bit lines are separated by one of the four local bit lines; and
a second multiplex circuit to selectively couple a second pair of the four local bit lines to the second global bit line.