US 6,982,433 B2
Gate-induced strain for MOS performance improvement
Thomas Hoffman, Hillsboro, Oreg. (US); Stephen M. Cea, Hillsboro, Oreg. (US); and Martin D. Giles, Hillsboro, Oreg. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Jun. 12, 2003, as Appl. No. 10/459,998.
Prior Publication US 2004/0253776 A1, Dec. 16, 2004
Int. Cl. H01L 29/06 (2006.01); H01L 31/007 (2006.01); H01L 31/109 (2006.01); H01L 31/0328 (2006.01); H01L 31/0336 (2006.01)
U.S. Cl. 257—18 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a device over the substrate including a gate electrode over a surface of the substrate; and
a straining material disposed over the gate electrode, the straining material having at least one of a lattice spacing that is different than a lattice spacing of the gate electrode, a coefficient of linear thermal expansion of the straining material that is different than a coefficient of linear thermal expansion of a material of the gate electrode, and an intrinsic stress in the straining material.