US 6,982,449 B2 | ||
Junction-isolated depletion mode ferroelectric memory devices | ||
Craig T. Salling, Plano, Tex. (US); and Brian W. Huber, Allen, Tex. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Aug. 26, 2004, as Appl. No. 10/926,470. | ||
Application 10/926470 is a division of application No. 10/306592, filed on Nov. 27, 2002, granted, now 6,876,022. | ||
Application 10/306592 is a division of application No. 09/652557, filed on Aug. 31, 2000, granted, now 6,515,889, filed on Feb. 04, 2003. | ||
Prior Publication US 2005/0024918 A1, Feb. 03, 2005 | ||
Int. Cl. H01L 31/119 (2006.01) |
U.S. Cl. 257—295 | 30 Claims |
1. A memory device, comprising:
an array of memory cells, wherein each memory cell comprises:
a control gate formed overlying a ferroelectric layer;
a first source/drain region having a first conductivity type;
a second source/drain region having the first conductivity type;
a channel region interposed between the first and second source/drain regions and having the first conductivity type; and
a well coupled to the second source/drain region and having a second conductivity type, wherein the second conductivity type
is opposite the first conductivity type and wherein the well is isolated from the control gate;
a plurality of word lines coupled to rows of memory cells of the array of memory cells through their control gates;
a plurality of program lines coupled to columns of memory cells of the array of memory cells through their first source/drain
regions;
a plurality of bit lines coupled to columns of memory cells of the array of memory cells through their wells;
a row decoder coupled to the array of memory cells; and
a column decoder coupled to the array of memory cells.
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