US 6,983,356 B2 | ||
High performance memory device-state aware chipset prefetcher | ||
Hemant G. Rotithor, Hillsboro, Oreg. (US); Randy B. Osborne, Beaverton, Oreg. (US); and Donald W. McCauley, Lakeway, Tex. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Dec. 19, 2002, as Appl. No. 10/325,795. | ||
Prior Publication US 2004/0123043 A1, Jun. 24, 2004 | ||
Int. Cl. G06F 12/00 (2006.01) |
U.S. Cl. 711—213 | 66 Claims |
1. A method of prefetching from a memory device, comprising:
determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate;
inserting prefetches to open pages before completing demand transactions if the memory bandwidth utilization (MBU) rate is
above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level; and
inserting prefetches to open pages after completing the demand transactions if the memory bandwidth utilization (MBU) rate
is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.
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