US 6,982,451 B1
Single event upset in SRAM cells in FPGAs with high resistivity gate structures
Martin L. Voogel, Los Altos, Calif. (US); Austin H. Lesea, Los Gatos, Calif. (US); Joseph J. Fabula, Tuscon, Ariz. (US); Carl H. Carmichael, Campbell, Calif. (US); Shahin Toutounchi, Pleasanton, Calif. (US); Michael J. Hart, Palo Alto, Calif. (US); Steven P. Young, Boulder, Colo. (US); Kevin T. Look, Fremont, Calif. (US); and Jan L. de Jong, Cupertino, Calif. (US)
Assigned to Xilinx, Inc., San Jose, Calif. (US)
Filed on Mar. 27, 2003, as Appl. No. 10/402,446.
Int. Cl. H01L 27/108 (2006.01)
U.S. Cl. 257—300 12 Claims
OG exemplary drawing
 
1. A memory device formed in an integrated circuit and having single event upset (SEU) resistant circuitry, comprising:
a pair of cross-coupled inverters, at least one of which has a gate structure comprising an SEU-hardening series resistance,
wherein the cross-coupled inverters are formed in a substrate and the SEU-hardening series resistance is formed in a layer above the substrate;
wherein the cross-coupled inverters form a configuration memory cell of an FPGA; and
wherein the gate structure comprises:
a polysilicon layer; and
a plug coupled to the polysilicon layer, the plug comprising a conductive layer and a contact dielectric layer, the contact dielectric layer further providing the SEU hardening series resistance.