US 6,982,465 B2 | ||
Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics | ||
Yukihiro Kumagai, Tsuchiura (Japan); Hiroyuki Ohta, Tsuchiura (Japan); Fumio Ootsuka, Ome (Japan); Shuji Ikeda, Kodaira (Japan); Takahiro Onai, Kokubunji (Japan); Hideo Miura, Tsuchiura (Japan); Katsuhiko Ichinose, Ome (Japan); and Toshifumi Takeda, Kodaira (Japan) | ||
Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
Appl. No. 10/433,786 PCT Filed Dec. 06, 2001, PCT No. PCT/JP01/10692 § 371(c)(1), (2), (4) Date Jun. 06, 2003, PCT Pub. No. WO02/47167, PCT Pub. Date Jun. 13, 2002. |
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Claims priority of application No. 2000-379785 (JP), filed on Dec. 08, 2000; application No. 2001-191612 (JP), filed on Jun. 25, 2001; and application No. 2001-342667 (JP), filed on Nov. 08, 2001. | ||
Prior Publication US 2004/0075148 A1, Apr. 22, 2004 | ||
Int. Cl. H01L 29/76 (2006.01) |
U.S. Cl. 257—369 | 16 Claims |
1. A semiconductor device comprising an n-channel field effect transistor and a p-channel field effect transistor both formed
on a substrate,
wherein said transistors each comprise an insulated film wrapping a gate electrode and extending to a location adjacent to
a source/drain area, and said insulated film is mainly composed of silicon nitride, and the thickness of said insulated film
of said n-channel field effect transistor differs from the thickness of said insulated film of said p-channel field effect
transistor.
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