US 6,982,905 B2 | ||
Method and apparatus for reading NAND flash memory array | ||
Dzung H. Nguyen, Fremont, Calif. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Oct. 09, 2003, as Appl. No. 10/682,585. | ||
Prior Publication US 2005/0078518 A1, Apr. 14, 2005 | ||
Int. Cl. G11C 16/04 (2006.01) |
U.S. Cl. 365—185.17 | 20 Claims |
1. A method for reading/verifying a NAND flash memory array comprising a column of memory cells having a first end controlled
by a select gate drain line and a second end controlled by a select gate source line, the method comprising:
decoding an input address signal to determine which cell to select; and
biasing the select gate drain and select gate source lines in an order responsive to a position of the selected cell in the
column.
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