US 6,983,402 B2
Computer device
Takashi Yoneda, Osaka (Japan); and Masahiko Matsumoto, Kyoto (Japan)
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan)
Filed on Dec. 10, 2001, as Appl. No. 10/6,134.
Claims priority of application No. 2000-375495 (JP), filed on Dec. 11, 2000.
Prior Publication US 2002/0073286 A1, Jun. 13, 2002
Int. Cl. G06F 11/00 (2006.01)
U.S. Cl. 714—48 9 Claims
OG exemplary drawing
 
1. A computer device comprising:
a CPU for outputting an address signal and also outputting an access signal twice for the same address signal;
a memory for storing a series of programs, the memory receiving the address signal and the access signal from the CPU and outputting a program located at an address corresponding to the address signal twice in response to the access signal;
a latch circuit for latching the program output from the memory, according to the access signal; and
a match detection circuit for comparing the two programs at the same address output from the memory, that is, a first-time program output from the latch circuit and a second-time program output from the memory, and detecting matching of the two programs,
wherein the CPU receives a comparison result signal from the match detection circuit, and outputs the access signal for the same address again if the matching of the programs fails, so that the match detection circuit performs comparison of a third-time program output from the memory with the second-time program output from the latch circuit.