US 6,983,394 B1
Method and apparatus for clock signal performance measurement
Shawn K. Morrison, San Jose, Calif. (US); Andrew K. Percey, Sunnyvale, Calif. (US); John D. Logue, Placerville, Calif. (US); James M. Simkins, Park City, Utah (US); and Nicholas J. Sawyer, Opio (France)
Assigned to Xilinx, Inc., San Jose, Calif. (US)
Filed on Jan. 24, 2003, as Appl. No. 10/351,033.
Int. Cl. G06F 1/04 (2006.01)
U.S. Cl. 713—500 40 Claims
OG exemplary drawing
 
30. A system for measuring jitter of an input signal, comprising:
a relative phase encoder, the relative phase encoder including a delay chain and flip-flops, the delay chain having a plurality of tap nodes, the plurality of tap nodes respectively connected to flip-flop delay inputs of the flip-flops for sampling the input signal to the delay chain, the relative phase encoder configured to receive a clock signal to first flip-flop clock inputs of the flip-flops, the relative phase encoder having an encoder respectively coupled to flip-flop outputs of the flip-flops and configured to provide encoded phase of the input signal relative to the clock signal responsive to the flip-flop outputs; and
a data compare circuit coupled to receive the encoded phase and configured to compare the encoded phase with a stored reference sample.