US 6,982,207 B2
Methods for filling high aspect ratio trenches in semiconductor layers
Jingyi Bai, Boise, Id. (US); Weimin Li, Boise, Id. (US); and William S. Budge, Homedale, Id. (US)
Assigned to Micron Technology, Inc., Boise, Id. (US)
Filed on Jul. 11, 2003, as Appl. No. 10/618,220.
Prior Publication US 2005/0009291 A1, Jan. 13, 2005
Int. Cl. H01L 21/76 (2006.01); H01L 21/336 (2006.01); H01L 21/4763 (2006.01); H01L 21/31 (2006.01)
U.S. Cl. 438—424 29 Claims
OG exemplary drawing
 
1. A method for filling a trench in a semiconductor layer located in a process chamber consisting of:
flowing a first gas flow into said process chamber;
forming a first plasma from said first gas flow;
applying a first RF bias to said semiconductor layer, wherein said first gas flow and said first RF bias are selected such that said trench is partially filled with a first layer of trench filling material at a first etch/dep ratio;
flowing a second gas flow into said process chamber;
forming a second plasma from said second gas flow; and
applying a second RF bias to said semiconductor layer; wherein:
said second gas flow and said second RF bias are selected such that said trench is filled with a second layer of trench filling material at a second etch/dep ratio; and
said first etch/dep ratio is selected to be higher than said second etch/dep ratio.