US 6,982,914 B2
Semiconductor memory device
Hirohisa Ohtsuki, Ashiya (Japan); and Toshikazu Suzuki, Nishinomiya (Japan)
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan)
Filed on Jan. 08, 2004, as Appl. No. 10/754,747.
Claims priority of application No. 2003-008791 (JP), filed on Jan. 16, 2003.
Prior Publication US 2004/0141395 A1, Jul. 22, 2004
Int. Cl. G11C 7/02 (2006.01)
U.S. Cl. 365—210 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory array including a plurality of memory cells;
a sense amplifier circuit for amplifying data read from selected memory cells in the memory array to bit lines;
a replica circuit including a plurality of replica cells having the same elements as those of the memory cells that outputs a signal at a level in accordance with a stage number to a common replica bit line; and
a sense amplifier control circuit for receiving the signal of the replica bit line to control a timing of a signal for starting the sense amplifier circuit,
wherein the replica circuit includes a switching circuit for switching the stage number of replica cells to be activated among the plurality of replica cells.