US 6,983,427 B2 | ||
Generating a logic design | ||
William R. Wheeler, Southborough, Mass. (US); and Matthew J. Adiletta, Worcester, Mass. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Aug. 29, 2001, as Appl. No. 9/942,102. | ||
Prior Publication US 2003/0046640 A1, Mar. 06, 2003 | ||
Int. Cl. G06F 17/50 (2006.01) |
U.S. Cl. 716—1 | 20 Claims |
1. A method of generating a logic design for use in designing an integrated circuit (IC), comprising:
generating a computer instruction;
importing the computer instruction from memory; and
embedding the computer instruction within a two-dimensional schematic representation of the logic design to produce a unified
database representation of the logic design, the computer instruction being devoid of declarations and entries to a sensitivity
list;
wherein the two-dimensional schematic representation includes a set of Register Transfer Diagrams (RTD).
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