US 6,983,350 B1
SDRAM controller for parallel processor architecture
William R. Wheeler, Southborough, Mass. (US); Bradley Burres, Cambridge, Mass. (US); Matthew J. Adiletta, Worcester, Mass. (US); and Gilbert Wolrich, Framingham, Mass. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Aug. 31, 1999, as Appl. No. 9/387,109.
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—151 21 Claims
OG exemplary drawing
 
18. A controller for a random access memory comprises:
an address and command queue that holds memory references from a plurality of microcontrol functional units;
a first read/write queue that holds memory references from a computer bus;
a second read/write queue that holds memory references from a core processor; and control logic including an arbiter that detects the fullness of each of the queues and a status of outstanding memory reference to select a memory reference from one of the queues, wherein the address and command queue comprises:
an even bank queue;
an odd bank queue;
an order queue;
wherein a microengine sorts memory references into odd bank and even bank references; and
wherein controller examines an optimized memory reference bit and if set, causes incoming reference requests to be sorted into either the even bank queue or the odd bank queue.