US 6,982,911 B2
Memory device with common row interface
Jong-Hoon Oh, Chapel Hill, N.C. (US)
Assigned to Infineon Technologies AG, Munich (Germany)
Filed on Mar. 18, 2004, as Appl. No. 10/805,024.
Prior Publication US 2005/0207258 A1, Sep. 22, 2005
Int. Cl. G11C 29/00 (2006.01)
U.S. Cl. 365—200 23 Claims
OG exemplary drawing
 
1. A semiconductor memory receiving an external address including an array address and a row address, the memory comprising:
N memory arrays, each memory array having an array address and a plurality of normal and redundant rows of memory cells;
a redundancy block providing a match signal having an active state when the external address matches one of a plurality of defective addresses, providing a redundant row address when the match signal has the active state, and providing a redirected array address comprising a redundant array address when the match signal has the active state and otherwise comprising the external array address; and
N local row control blocks, each associated with a different one of the N memory arrays, wherein the local row control block associated with the memory array whose array address matches the redirected array address opens a redundant row of memory cells for access based on the redundant row address when the match signal has the active state and otherwise opens a normal row of memory cells for access based on the external row address.