US 6,982,477 B2 | ||
Integrated circuit | ||
Alberto O. Adan, Ikoma (Japan) | ||
Assigned to Sharp Kabushiki Kaisha, Osaka (Japan) | ||
Filed on Apr. 02, 2004, as Appl. No. 10/815,952. | ||
Claims priority of application No. 2003-102118 (JP), filed on Apr. 04, 2003. | ||
Prior Publication US 2004/0195692 A1, Oct. 07, 2004 | ||
Int. Cl. H01L 29/72 (2006.01) |
U.S. Cl. 257—659 | 17 Claims |
1. An integrated circuit, comprising:
a target element; and
a metal fence provided so as to surround the target element,
the metal fence including (i) a lamination of metal wire layers for forming an electromagnetic isolation structure and (ii)
a plurality of vias for connecting the metal wire layers with each other,
the metal fence satisfying
d≤λ/8,
WF≧5δ, and
L≤λ/20,
where δ is a skin depth of an electromagnetic wave, c is a velocity of light, f is an operating frequency of the integrated
circuit, d=Area1/2 (where Area is an area of a circuit region to be protected), WF is a surrounding-line width of the metal fence, L is an interval
between the vias, and λ=c/f is a wavelength of a signal.
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