US 6,982,486 B2
Cavity ball grid array apparatus having improved inductance characteristics and method of fabricating the same
Jerry M. Brooks, Caldwell, Id. (US); and Steven G. Thummel, Boise, Id. (US)
Assigned to Micron Technology, Inc., Boise, Id. (US)
Filed on May 17, 2004, as Appl. No. 10/847,705.
Application 10/847705 is a continuation of application No. 10/011525, filed on Nov. 05, 2001, granted, now 6,740,971, filed on May 25, 2004.
Application 10/011525 is a continuation of application No. 09/567633, filed on May 09, 2000, granted, now 6,326,244, filed on Dec. 04, 2001.
Application 09/567633 is a continuation of application No. 09/146643, filed on Sep. 03, 1998, granted, now 6,084,297, filed on Jul. 04, 2000.
Prior Publication US 2004/0207064 A1, Oct. 21, 2004
Int. Cl. H01L 23/053 (2006.01); H01L 23/48 (2006.01); H01L 23/02 (2006.01); H01L 21/00 (2006.01)
U.S. Cl. 257—738 28 Claims
OG exemplary drawing
 
1. A semiconductor die package, comprising:
a package substrate having at least one conductive trace on a surface thereof;
a semiconductor die attached to the package substrate;
a layer of anisotropically conductive material disposed over the surface of the package substrate and defining a cavity surrounding the semiconductor die; and
a conductive reference plane element disposed over the layer of anisotropically conductive material, wherein the layer of anisotropically conductive material provides an electrical connection between the conductive reference plane element and the at least one conductive trace.