US 6,983,431 B2 | ||
Simultaneous placement of large and small cells in an electronic circuit | ||
Ross A. Donelly, Sunnyvale, Calif. (US); William C. Naylor, San Jose, Calif. (US); and Jason R. Woolever, Sunnyvale, Calif. (US) | ||
Assigned to Synopsys, Inc., Mountain View, Calif. (US) | ||
Filed on May 09, 2003, as Appl. No. 10/434,736. | ||
Prior Publication US 2004/0225971 A1, Nov. 11, 2004 | ||
Int. Cl. G06F 17/50 (2006.01) |
U.S. Cl. 716—2 | 13 Claims |
1. A method of removing overlap among cells of an integrated circuit comprising:
a) synthesizing a design of said integrated circuit;
b) placing said cells within an integrated circuit area boundary;
c) moving one of said cells in one direction of a linear dimension until said one of said cells abuts selectively an edge
of said integrated circuit or another cell
d) combining two of said cells which abut one another into a combination cell; and
e) moving said combination cell so as to minimize the square of the displacement from the original position of a cell multiplied
by the size of said cell for both cells which comprise said combination cell.
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