US 6,983,191 B2
Semiconductor manufacturing line availability evaluating system and design system
Yuuichi Mikata, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Sep. 24, 2004, as Appl. No. 10/948,166.
Claims priority of application No. 2003-336248 (JP), filed on Sep. 26, 2003.
Prior Publication US 2005/0107904 A1, May 19, 2005
Int. Cl. G06F 19/00 (2006.01)
U.S. Cl. 700—121 19 Claims
OG exemplary drawing
 
1. An availability evaluating system for obtaining an availability of a semiconductor manufacturing line in which it is virtually assumed that a unit group having one or more tool units are serially connected in time series according to a processing event, the system comprising:
a first unit configured to calculate an incidence probability Xi (i=1 to k) in combination by applying a probability of tool operation and a probability of tool stoppage to all combinations “k” in which at least a line fabrication availability is not zero, of the combinations of operation and stoppage of tools each configuring the semiconductor manufacturing line and by obtaining a product of the probabilities of all the tools; and
a second unit configured to, when a product between an incidence probability Xi of a combination and a fabrication availability Yi of the combination is defined as a probability converted fabrication availability with respect to each of the combinations, calculate as a line availability a value of Q=Σ(i=1 to k)X1×Y1/F obtained by dividing a sum of probability converted fabrication availabilities of the combinations by a fabrication availability F determined during a 100% availability.