US 6,983,437 B2
Timing verification, automated multicycle generation and verification
Mogens Lauritzen, Los Altos, Calif. (US); Gaurav Garg, Sunnyvale, Calif. (US); and Umesh M. Nair, Newark, Calif. (US)
Assigned to Sun Microsystems, Inc., Santa Clara, Calif. (US)
Filed on Nov. 05, 2003, as Appl. No. 10/702,796.
Prior Publication US 2005/0097487 A1, May 05, 2005
Int. Cl. G06F 17/50 (2006.01)
U.S. Cl. 716—6 18 Claims
OG exemplary drawing
 
1. A method for generating consistent functional and timing definitions comprising:
providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design;
transforming the common source description to a functional definition;
monitoring a functional simulation of the integrated circuit chip design using the functional definition;
transforming the common source description to a timing definition, the transforming the common source description to the timing definition including
transforming the common source description to an intermediate timing definition; and,
transforming the intermediate timing definition to the timing definition; and,
performing a timing analysis of the integrated circuit chip design using the timing definition.