US 6,983,388 B2
Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines
Stefanos Kaxiras, Jersey City, N.J. (US); Philip W. Diodato, Asbury, N.J. (US); Hubert Rae McLellan, Jr., Summit, N.J. (US); and Girija Narlikar, Jersey City, N.J. (US)
Assigned to Agere Systems Inc., Allentown, Pa. (US)
Filed on May 25, 2001, as Appl. No. 9/865,847.
Claims priority of provisional application 60/243173, filed on Oct. 25, 2000.
Prior Publication US 2002/0049918 A1, Apr. 25, 2002
Int. Cl. G06F 1/32 (2006.01)
U.S. Cl. 713—324 35 Claims
OG exemplary drawing
 
1. A cache memory, comprising:
a plurality of cache lines for storing a value from main memory; and
a timer associated with each of said plurality of cache lines, each of said timers configured to control a signal that removes power to said associated cache line after a decay interval.