US 6,982,995 B2 | ||
Multi-channel SONET/SDH desynchronizer | ||
Predrag Sava Acimovic, Burnaby (Canada) | ||
Assigned to PMC-Sierra, Inc., (Canada) | ||
Filed on Apr. 24, 2001, as Appl. No. 9/840,110. | ||
Claims priority of application No. 2307044 (CA), filed on Apr. 28, 2000. | ||
Prior Publication US 2002/0021719 A1, Feb. 21, 2002 | ||
Int. Cl. H04J 3/06 (2006.01) |
U.S. Cl. 370—518 | 17 Claims |
1. A desynchronizer for desynchronizing a plurality of data channels of SONET/SDH data signals, comprising:
(a) a plurality of first in first out buffer (FIFO) blocks, one for each of said data channels, said FIFO blocks each having
respective FIFO read and write address outputs, a gapped clock input operative in response to gapped clock signals, to store
input data extracted from a SONET/SDH frame;
(b) an arithmetic unit having a phase word output and inputs coupled to the read and write address outputs of each of said
FIFO blocks, operative to calculate an address difference of the read and write addresses for each of said FIFO blocks and
a phase locked loop (PLL) phase increment value, which depends on the address difference and a pointer adjustment phase difference
and adding or subtracting a small number to provide a total phase increment from said phase word output for each of said FIFO
blocks;
(c) an endless phase modulator common control block coupled to an output of said arithmetic unit operative to produce delay
tap selection signals in response to corresponding total phase increment from said arithmetic unit;
(d) an oscillator; and
(e) an endless phase modulator coupled to an output of said endless phase modulator common control block and to said oscillator
and operative in response to said delay tap selection signals to generate clock signals frequency shifted from a frequency
of said oscillator and to apply said clock signals to respective desynchronized clock inputs of said FIFO buffer blocks and
to thereby clock out desynchronized data signals from said FIFO buffer blocks.
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