US 6,983,234 B1
System and method for validating processor performance and functionality
Sudheendra Hangal, Sunnyvale, Calif. (US); and James M. O'Connor, Union City, Calif. (US)
Assigned to Sun Microsystems, Inc., Palo Alto, Calif. (US)
Filed on Mar. 20, 2000, as Appl. No. 9/531,026.
Claims priority of provisional application 60/127368, filed on Apr. 01, 1999.
Int. Cl. G06F 17/50 (2006.01)
U.S. Cl. 703—14 10 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising the steps of:
executing a program on a high level simulator of a processor; thereafter
dividing the program into a plurality of independent code fragments such that a destination branch of an instruction in each code fragment falls within that code fragment; thereafter
establishing a plurality of checkpoints; wherein each of the plurality of checkpoints is established along a beginning point of a different one of the code fragments; thereafter
saving state data at each of said checkpoints; wherein said state data comprises:
program counter contents of said processor;
register contents of said processor;
cache memory contents of said processor;
main memory contents of processor; and
branch prediction contents of said processor; thereafter
executing instructions in said program on a plurality of low level simulators of said processor in parallel, starting each of said low level simulators at a corresponding checkpoint with corresponding state data associated with said corresponding checkpoint, wherein said executing instructions step further comprises the steps of:
loading each of said low level simulators with said program;
initializing each of said low level simulators at said corresponding checkpoint with said corresponding state data associated with said corresponding checkpoint; and
executing said program on said low level simulator up to a certain point in said program; and thereafter
generating functional data to validate functionality of the processor.