US 6,982,900 B2
Semiconductor integrated circuit device
Osamu Hirabayashi, Tokyo (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on May 26, 2004, as Appl. No. 10/853,193.
Claims priority of application No. 2004-029556 (JP), filed on Feb. 05, 2004.
Prior Publication US 2005/0174833 A1, Aug. 11, 2005
Int. Cl. G11C 11/00 (2006.01)
U.S. Cl. 365—154 18 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device comprising:
a data bit storage memory which stores data bits;
a code bit storage memory which stores code bits, the code bit storage memory being controlled independently from the data bit storage memory; and
an ECC circuit which corrects an error of at least one bit contained in one of the data bits and code bits by use of the data bit and code bit;
wherein an operation of writing the code bit corresponding to the data bit into the code bit storage memory is performed at least one cycle after the data bit is written into the data bit storage memory, when a data write command is received.