US 6,982,913 B2
Data read circuit for use in a semiconductor memory and a memory thereof
Hyung-Rok Oh, Sungnam-si (Korea, Republic of); Woo-Yeong Cho, Yongin-si (Korea, Republic of); and Choong-Keun Kwak, Suwon-si (Korea, Republic of)
Assigned to Samsung Electronics, Co., Ltd., Suwon-si (Korea, Republic of)
Filed on Sep. 17, 2004, as Appl. No. 10/943,300.
Claims priority of application No. 10-2003-0065023 (KR), filed on Sep. 19, 2003.
Prior Publication US 2005/0030814 A1, Feb. 10, 2005
Int. Cl. G11C 7/00 (2006.01)
U.S. Cl. 365—203 20 Claims
OG exemplary drawing
 
1. A data read circuit for use in a semiconductor memory device having a memory cell array, the memory cell array having a plurality of unit cells, the data read circuit comprising:
a selector for selecting one of the plurality of unit cells in response to an address signal;
a clamping unit connected between a bit line coupled with the selected unit cell and a sensing node, the clamping unit for supplying a clamp voltage having a level for a read operation to the bit line of the selected unit cell in response to a clamp control signal;
a precharge unit for precharging the sensing node to a voltage having a power source level in response to a control signal of a first state applied during a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line connected to the selected unit cell in response to a control signal of a second state applied during a data sensing mode; and
a sense amplifier unit for comparing a level of the sensing node with a reference level and for sensing data stored in the selected unit cell, when the control signal of the second state is applied to the precharge unit.