US 6,982,457 B2 | ||
Semiconductor devices, and electronic systems comprising semiconductor devices | ||
Arup Bhattacharyya, Essex Junction, Vt. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Feb. 17, 2004, as Appl. No. 10/781,588. | ||
Application 10/781588 is a continuation of application No. 10/364710, filed on Feb. 10, 2003, granted, now 6,713,810. | ||
Prior Publication US 2004/0159880 A1, Aug. 19, 2004 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H01L 29/788 (2006.01) |
U.S. Cl. 257—315 | 23 Claims |
1. A semiconductor device comprising:
a crystalline layer separated from a substrate by a first insulative material; the crystalline layer comprising silicon/germanium;
a floating charge trapping media over the crystalline layer;
a pair of source/drain regions proximate the charge trapping media and extending into the crystalline layer such that at least
a portion of the source/drain regions are within the crystalline layer; the portion of the source/drain regions within the
crystalline layer being contained within a single crystal of the silicon/germanium;
a second insulative material over the charge trapping media; and
a control gate over the second insulative material.
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