US 7,320,935 B2
Semiconductor device using an interconnect
Jihperng Leu, Portland, Oreg. (US); and Christopher D. Thomas, Aloha, Oreg. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Aug. 05, 2003, as Appl. No. 10/635,892.
Application 10/635892 is a division of application No. 10/025030, filed on Dec. 19, 2001, granted, now 6,605,874.
Prior Publication US 2004/0026786 A1, Feb. 12, 2004
Int. Cl. H01L 21/44 (2006.01)
U.S. Cl. 438—636  [257/734; 257/E21.584] 17 Claims
OG exemplary drawing
 
1. A process of forming a metallization comprising:
forming a first interlayer dielectric (ILD) layer above a substrate;
forming a first recess in the first ILD layer;
filling the first recess with a first interconnect;
forming a conductive first diffusion barrier layer above and on the first interconnect;
forming an upper ILD layer above the first conductive diffusion barrier layer;
forming an upper recess in the upper ILD layer to expose the first conductive diffusion barrier layer;
forming an upper interconnect in the upper recess; and
forming a conductive upper diffusion barrier layer above and on the upper interconnect.