US 7,321,132 B2
Multi-layer structure for use in the fabrication of integrated circuit devices and methods for fabrication of same
Kevin L. Robinson, Clay, N.Y. (US); Larry Witkowski, Plano, Tex. (US); and Ming-Yih Kao, Dallas, Tex. (US)
Assigned to Lockheed Martin Corporation, Bethesda, Md. (US)
Filed on Mar. 15, 2005, as Appl. No. 11/80,293.
Prior Publication US 2006/0208279 A1, Sep. 21, 2006
Int. Cl. H01L 29/06 (2006.01); H01L 29/201 (2006.01); H01L 29/732 (2006.01); H01L 21/338 (2006.01)
U.S. Cl. 257—12  [257/90; 257/94; 257/183; 438/167; 438/172; 438/186; 438/191] 14 Claims
OG exemplary drawing
 
1. A multi-layer structure for use in the fabrication of integrated circuit devices, comprising:
a buffer layer on a substrate;
a channel layer on said buffer layer;
a spacer layer on said channel layer;
a first Schottky layer on said spacer layer;
a second Schottky layer overlying said first Schottky layer;
a third Schottky layer overlying said second Schottky layer;
a contact layer overlying said third Schottky layer;
said structure having defined therein:
a first etch-stop intermediate said first Schottky layer and said second Schottky layer;a second etch-stop intermediate said second Schottky layer and said third Schottky layer; anda third etch-stop intermediate said contact layer and said third Schottky layer.