US 7,321,152 B2
Thin-film transistor and method of fabricating the same
Shigeto Maegawa, Tokyo (Japan); Takashi Ipposhi, Tokyo (Japan); Toshiaki Iwamatsu, Tokyo (Japan); Shigenobu Maeda, Tokyo (Japan); Il-Jung Kim, Tokyo (Japan); Kazuhito Tsutsumi, Tokyo (Japan); Hirotada Kuriyama, Tokyo (Japan); Yoshiyuki Ishigaki, Toyko (Japan); Motomu Ukita, Tokyo (Japan); and Toshiaki Tsutsumi, Tokyo (Japan)
Assigned to Renesas Technology Corp., Tokyo (Japan)
Filed on Aug. 04, 2006, as Appl. No. 11/498,800.
Application 11/498800 is a division of application No. 11/078581, filed on Mar. 14, 2005.
Application 11/078581 is a continuation of application No. 08/850631, filed on May 02, 1997, granted, now 7,112,854.
Claims priority of application No. 8-306626 (JP), filed on Nov. 18, 1996.
Prior Publication US 2006/0267012 A1, Nov. 30, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/76 (2006.01); H01L 31/113 (2006.01)
U.S. Cl. 257—382  [257/758; 257/E29.76; 257/E31.113] 4 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a first insulating layer formed over said semiconductor substrate;
a first plug being provided in a first contact hole formed in said first insulating layer;
a second insulating layer formed over said first insulating layer;
a second contact hole formed in said second insulating layer;
an element formed over said second insulting layer; and
a second plug being provided in said second contact hole and through said element,
wherein said second plug has a bottom face with a first bottom face portion in contact with a top face portion of said first plug and a second bottom face portion in contact with said first insulation layer.