US 7,321,517 B2 | ||
Semiconductor memory device | ||
Hitoshi Ikeda, Kawasaki (Japan); Kaoru Mori, Kawasaki (Japan); and Yoshiaki Okuyama, Kawasaki (Japan) | ||
Assigned to Fujitsu Limited, Kawasaki (Japan) | ||
Filed on Oct. 28, 2005, as Appl. No. 11/260,200. | ||
Claims priority of application No. 2005-190298 (JP), filed on Jun. 29, 2005. | ||
Prior Publication US 2007/0002648 A1, Jan. 04, 2007 | ||
Int. Cl. G11C 7/00 (2006.01) |
U.S. Cl. 365—194 [365/201; 365/203; 365/230.03; 365/230.06] | 13 Claims |
1. A semiconductor memory device comprising:
a plurality of memory cells provided at positions where a plurality of word lines and a pair of bit lines intersect with each
other;
an equalizing circuit connecting said pair of bit lines to each other and connecting said pair of bit lines to a precharge
voltage line, in response to activation of an equalizing control signal;
an equalizing control circuit deactivating said equalizing control signal in response to activation of a first timing signal;
a word line driving circuit activating one of said word lines in response to activation of a second timing signal; and
a timing control circuit having a first signal generating circuit which generates said first timing signal and a second signal
generating circuit which activates said second timing signal after said equalizing control signal is deactivated in response
to activation of said first timing signal, wherein
said second signal generating circuit includes a delay control circuit delaying an activation timing of said second timing
signal in a test mode from an activation timing of said second timing signal in a normal mode.
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