US 7,321,651 B2 | ||
High frequency circuit capable of error detection and correction of code patterns running at full speed | ||
David W. Boerstler, Round Rock, Tex. (US); Eskinder Hailu, Austin, Tex. (US); and Jieming Qi, Austin, Tex. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Nov. 12, 2004, as Appl. No. 10/988,285. | ||
Prior Publication US 2006/0117236 A1, Jun. 01, 2006 | ||
Int. Cl. H03K 21/40 (2006.01) |
U.S. Cl. 377—30 [377/28; 714/37; 714/40] | 18 Claims |
1. A high frequency circuit for generating an error detection state and correction of code patterns running at full speed,
comprising:
a shadow register means having a plurality of pattern inputs and a plurality of shadow register outputs;
a serial/parallel shift register having a plurality of inputs, wherein each input of the plurality of inputs is at least connected
to at least one shadow register outputs, and wherein the serial/parallel shift register is at least configured to be selectively
programmable to alternate between a serial mode and a parallel mode;
a plurality of comparators each having a pair of inputs, wherein each input of each comparator is at least configured to be
coupled to an output of the serial/parallel shift register;
at least one logic gate that is at least configured to receive an output from each comparator of the plurality of comparators;
and
output circuitry that is at least configured to receive an output of the logic gate to generate a signal that is functionally
related to the error detection state.
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