US 7,321,404 B2 | ||
Liquid crystal display device and a manufacturing method of the same | ||
Kiyohiro Kawasaki, Osaka (Japan) | ||
Assigned to AU Optronics Corporation, Hsin-chu (Taiwan) | ||
Filed on Oct. 14, 2004, as Appl. No. 10/963,801. | ||
Claims priority of application No. 2004-021288 (JP), filed on Jan. 29, 2004. | ||
Prior Publication US 2005/0168666 A1, Aug. 04, 2005 | ||
Int. Cl. G02F 1/133 (2006.01); G02F 1/1343 (2006.01); H01L 29/04 (2006.01) |
U.S. Cl. 349—43 [349/139; 349/47; 257/59; 257/72] | 9 Claims |
1. A liquid crystal display device, with at least the following characteristics in a liquid crystal display device that is
filled with liquid crystals between 1) a primary transparent insulating substrate that aligns, in a 2-dimensional matrix,
unit pixels that have on a principal plane at least a) an insulating gate type transistor, b) scanning lines that also work
as gate electrodes and signal lines that also work as source wires for the said insulated gate type transistor, and c) pixel
electrodes that are connected to drain wires and 2) a secondary transparent insulating substrate or color filter that faces
said primary transparent insulating substrate, comprising:
I) a laminate of a transparent conductive layer and a primary metal layer as gate electrodes, scanning lines, and conductive
pixel electrodes on the principal plane of a primary transparent insulating substrate;
II) an island-like channel layer through a gate insulating layer above the gate electrodes;
III) a protective insulating layer narrower than the gate electrodes on the said channel layer;
IV) a plurality of openings self aligned with said island-like channel layer, in the gate insulating layer on said pixel electrodes
within each opening;
V) a pair of semiconductor layers as the source-drain of the insulating gate type transistor, on parts of said protective
insulating layer and on the channel layer;
VI) a plurality of source wires and drain wires consisting of one or more secondary metal layers and a heat resistant metal
layer on said semiconductor layers, gate insulating layer and parts of the pixel electrodes within said openings; and
VI) a passivation insulating layer on said source/drain wires.
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