US 7,320,914 B1
System and method for gate formation in a semiconductor device
Hajime Wada, Sunnyvale, Calif. (US); and Jaeyong Park, Sunnyvale, Calif. (US)
Assigned to Spansion LLC, Sunnyvale, Calif. (US)
Filed on Feb. 23, 2005, as Appl. No. 11/62,629.
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—260  [438/596; 438/655; 257/E21.622] 18 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a first layer over a substrate;
forming a second layer over the first layer;
forming a mask over the second layer;
forming spacers adjacent opposite side surfaces of the mask;
etching the second layer to form at least one memory cell stack;
forming a dielectric layer over the memory device;
etching the dielectric layer to expose at least an upper surface of the at least one memory cell stack;
removing the mask; and
forming a silicide region on the second layer in the at least one memory cell stack,
wherein the silicide region in each memory cell stack is bounded by the spacers.