US 7,321,991 B2
Semiconductor memory device having advanced test mode
Yong-Bok An, Ichon-shi (Korea, Republic of)
Assigned to Hynix Semiconductor Inc., (Korea, Republic of)
Filed on Jun. 30, 2004, as Appl. No. 10/882,740.
Claims priority of application No. 10-2004-0001824 (KR), filed on Jan. 10, 2004; and application No. 10-2004-0018919 (KR), filed on Mar. 19, 2004.
Prior Publication US 2005/0166097 A1, Jul. 28, 2005
Int. Cl. G06F 11/00 (2006.01)
U.S. Cl. 714—42 11 Claims
OG exemplary drawing
 
1. An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode, the apparatus comprising:
an internal address generator for receiving an external bank address and generating internal bank addresses based on the external bank address in response to a compress test signal and a bank interleaving test signal;
a read operation testing block for receiving the internal bank addresses and testing a read operation of at least one bank selected by the internal bank addresses in response to an additive latency signal, the compress test signal and the bank interleaving test signal; and
a write operation testing block for receiving the internal bank addresses and testing a write operation of the selected banks,
wherein, in the compress test mode, the plurality of banks are simultaneously activated or selectively activated in response to the bank interleaving test signal.