US 7,322,002 B2
Erasure pointer error correction
Brady L. Keays, Half Moon Bay, Calif. (US); Shuba Swaminathan, Los Gatos, Calif. (US); and William H. Radke, San Francisco, Calif. (US)
Assigned to Micron Technology, Inc., Boise, Id. (US)
Filed on May 26, 2004, as Appl. No. 10/854,445.
Prior Publication US 2005/0268203 A1, Dec. 01, 2005
Int. Cl. G11C 29/00 (2006.01)
U.S. Cl. 714—763  [714/784; 714/777; 714/783; 714/781] 87 Claims
OG exemplary drawing
 
1. A memory system, comprising:
at least one memory device, wherein the at least one memory device contains a memory array with a plurality of memory cells arranged in one or more data segments, where each data segment contains an ECC code; and
a memory control circuit coupled to the at least one memory device, wherein the memory control circuit comprises,
a data buffer,
a host transfer circuit coupled to the data buffer, and
one or more ECC checker circuits, where the data buffer and the one or more ECC checker circuits are coupled to receive a selected read data segment;
wherein N is a maximum number of bad bits recorded for each segment of the at least one memory device; and
wherein the memory control circuit is adapted to correct the selected read data segent as it is read from the at least one memory device utilizing the one or more ECC checker circuits such that the one or more ECC checker circuits evaluate the selected read data segment with differing states of the N bad bits and where the memory control circuit selects the state of the N bad bits and selected read data segment that correctly evaluated in an ECC checker to transfer through the host transfer circuit.