US 7,320,916 B2 | ||
Manufacturing method of semiconductor device | ||
Hirotoshi Kubo, Gunma (Japan); Yasuhiro Igarashi, Kumagaya (Japan); and Masahiro Shibuya, Gifu (Japan) | ||
Assigned to Sanyo Electric Co., Ltd., Osaka (Japan); and Gifu Sanyo Electronics Co., Ltd., Gifu (Japan) | ||
Filed on Sep. 29, 2004, as Appl. No. 10/952,381. | ||
Claims priority of application No. 2003-380308 (JP), filed on Nov. 10, 2003; and application No. 2004-223228 (JP), filed on Jul. 30, 2004. | ||
Prior Publication US 2005/0106843 A1, May 19, 2005 | ||
Int. Cl. H01L 21/336 (2006.01) |
U.S. Cl. 438—268 [257/E21.42] | 8 Claims |
1. A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate;
performing a first ion implantation into the substrate to form a p-type impurity diffusion region;
performing a second ion implantation into the substrate to form an n-type impurity diffusion region;
forming an interlayer insulating film on the p-type impurity diffusion region and the n-type impurity diffusion region after
the first and second ion implantations;
forming a contact hole in the interlayer insulating film to expose at least part of n-type impurity diffusion region and part
of the p-type impurity diffusion region;
performing a third ion implantation into the exposed p-type impurity diffusion region and the exposed n-type impurity diffusion
region through the contact hole of the interlayer insulating film, the third ion implantation being of a p-type impurity;
and
depositing a high melting point metal layer on the interlayer insulating film so that the high melting point metal layer is
connected with at least the p-type impurity diffusion region through the contact hole of the interlayer insulating film.
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