US 7,321,259 B1
Programmable logic enabled dynamic offset cancellation
Sergey Yuryevich Shumarayev, San Leandro, Calif. (US)
Assigned to Altera Corporation, San Jose, Calif. (US)
Filed on Oct. 06, 2005, as Appl. No. 11/245,581.
Int. Cl. H03F 1/02 (2006.01); H04B 1/04 (2006.01)
U.S. Cl. 330—9  [330/253; 327/307; 455/299; 455/127] 29 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a buffer circuit having an offset cancellation circuit configured to receive an offset control signal;
programmable logic coupled to the buffer circuit and configured to monitor one or more signal offsets of the integrated circuit and to generate the offset control signal in response thereto; and
a signal receiving circuit electrically connected between the offset cancellation circuit and the programmable logic,
wherein the offset control signal generated by the programmable logic can compensate for offset in the buffer circuit, and wherein the signal receiving circuit is configured to amplify signals received from the offset cancellation circuit.