US 7,320,927 B2
In situ hardmask pullback using an in situ plasma resist trim process
Juanita DeLoach, Plano, Tex. (US); and Brian A. Smith, Plano, Tex. (US)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Oct. 20, 2003, as Appl. No. 10/689,177.
Prior Publication US 2005/0085047 A1, Apr. 21, 2005
Int. Cl. H01L 21/762 (2006.01)
U.S. Cl. 438—444  [438/424; 438/438; 438/700; 438/701; 438/713; 257/E21.546] 20 Claims
OG exemplary drawing
 
1. A process of fabricating an integrated circuit, comprising:
forming an opening in a substrate through a patterned photoresist layer and a hardmask layer located over said substrate with a plasma;
trimming said photoresist layer with a plasma to create an exposed portion of said hardmask layer;
removing said exposed portion with a plasma to create a trench guide opening; and
after removing said exposed portion, creating a trench through said trench guide opening with a plasma.