US 7,321,612 B2
Bit stream conditioning circuit having adjustable PLL bandwidth
Davide Tonietto, Laguna Niguel, Calif. (US); and Ali Ghiasi, Cupertino, Calif. (US)
Assigned to Broadcom Corporation, Irvine, Calif. (US)
Filed on Apr. 17, 2003, as Appl. No. 10/418,035.
Claims priority of provisional application 60/397599, filed on Jul. 22, 2002.
Prior Publication US 2004/0022303 A1, Feb. 05, 2004
Int. Cl. H04B 1/38 (2006.01)
U.S. Cl. 375—219  [342/151; 355/337.1; 370/395.62; 379/340; 379/398; 398/155; 708/323] 19 Claims
OG exemplary drawing
 
1. A high-speed serial bit stream interface that communicatively couples a line side media to a communication Application Specific Integrate Circuit (ASIC), the high-speed serial bit stream interface comprising:
a line side interface that communicatively couples to the line side media, that receives a RX signal therefrom, and that transmits a conditioned TX signal thereto;
a board side interface that communicatively couples to the communication ASIC, that receives a TX signal therefrom and that transmits a conditioned RX signal thereto;
a RX signal conditioning circuit communicatively coupled between an RX portion of the line side interface and an RX portion of the board side interface;
a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface;
wherein the RX signal conditioning circuit and the TX signal conditioning circuit operate on a serviced signal including the RX signal and the TX signal, respectively, and each of the RX signal conditioning circuit and the TX signal conditioning circuit include:
a limiting amplifier that receives the respective serviced signal and that amplifies the respective serviced signal to produce the respective serviced signal in a desired output range; and
a clock and data recovery circuit having an adjustable Phase Locked Loop (PLL) bandwidth that communicatively couples to the output of the limiting amplifier and receives, recovers, and reclocks the respective serviced signal; and
wherein the PLL bandwidth of the clock and data recovery circuit servicing the RX signal and the PLL bandwidth of the clock and data recovery circuit servicing the TX signal are separately controlled based upon respective serviced signal characteristics.