US 7,321,642 B2 | ||
Synchronization symbol re-insertion for a decision feedback equalizer combined with a trellis decoder | ||
Shidong Chen, Palatine, Ill. (US); Jilian Zhu, Palatine, Ill. (US); and Xiaojun Yang, Palatine, Ill. (US) | ||
Assigned to Micronas Semiconductors, Inc., Palatine, Ill. (US) | ||
Filed on Apr. 04, 2003, as Appl. No. 10/407,404. | ||
Claims priority of provisional application 60/370380, filed on Apr. 05, 2002. | ||
Claims priority of provisional application 60/370413, filed on Apr. 05, 2002. | ||
Prior Publication US 2003/0214976 A1, Nov. 20, 2003 | ||
Int. Cl. H04L 27/06 (2006.01) |
U.S. Cl. 375—341 [375/229; 375/354; 375/316; 375/265] | 5 Claims |
1. A synchronization symbol re-inserter for use in a symbol decoder, comprising:
a trellis decoder, including;
a plurality of decoding stages for decoding encoded data symbols, each decoding stage having as output intermediate decoded
symbols; and
a mirrored symbol delay line, including;
a plurality of multiplexers, each multiplexer providing multiplexer output symbols, and each multiplexer receiving as input
the intermediate decoded symbols from a following stage of the trellis decoder and the intermediate decoded symbols from a
current stage of the trellis decoder; a plurality of delay devices, each delay device receiving as input the multiplexer output
symbols from a selected one of the multiplexers and providing corresponding delayed multiplexer output symbols, the delayed
multiplexer output symbols of each delay device other than the multiplexer output symbols from a final one of the plurality
of multiplexers being fed to a following multiplexer; and
where when the delayed multiplexer output symbol of one of the plurality of delay devices is a synchronization symbol a following
one of the plurality of multiplexers selects the synchronization symbol delayed by the corresponding delay device at the output
of the mirrored symbol delay line, and otherwise the plurality of multiplexers provide the intermediate symbol from each of
the current stages of the trellis decoder at the output of the mirrored symbol delay line.
|