US 7,320,907 B2
Method for controlling lattice defects at junction and method for forming LDD or S/D regions of CMOS device
Ping-Pang Hsieh, Siaosinying (Taiwan); and Ji-Fu Kung, Miaoli (Taiwan)
Assigned to United Microelectronics Corp., Hsinchu (Taiwan)
Filed on Nov. 29, 2004, as Appl. No. 11/157.
Prior Publication US 2006/0115969 A1, Jun. 01, 2006
Int. Cl. H01L 21/84 (2006.01)
U.S. Cl. 438—166  [438/154; 438/301] 19 Claims
OG exemplary drawing
 
1. A method for controlling lattice defects at a junction, used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step, and comprising:
performing an extra implantation step to increase the stress in the substrate apart from a position of the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction, wherein the extra implantation step is performed before the ion implantation step for forming the junction.