US 7,321,368 B2
Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory
Jefferson Eugene Owen, Freemont, Calif. (US); Raul Zegers Diaz, Palo Alto, Calif. (US); and Osvaldo Colavin, Tucker, Ga. (US)
Assigned to STMicroelectronics, Inc., Carrollton, Tex. (US)
Filed on Jun. 19, 2002, as Appl. No. 10/174,918.
Application 10/174918 is a continuation of application No. 09/539729, filed on Mar. 30, 2000, granted, now 6,427,194, filed on Mar. 04, 2002.
Application 09/539729 is a continuation of application No. 08/702910, filed on Aug. 26, 1996, granted, now 6,058,459, filed on May 02, 2000.
Prior Publication US 2002/0180743 A1, Dec. 05, 2002
Int. Cl. G06F 15/167 (2006.01); G09G 5/36 (2006.01); G09G 5/39 (2006.01)
U.S. Cl. 345—541  [345/542; 345/531; 345/547] 25 Claims
OG exemplary drawing
 
1. An electronic system comprising:
a main memory having stored therein data corresponding to images to be decoded and also decoded data corresponding to images that have previously been decoded;
a bus coupled to the memory;
a decoder coupled to the bus for receiving compressed images and for outputting data for displaying the decoded images on a display device, the decoder receiving data from the main memory corresponding to at least one previously decoded image and to a current image to be decoded and outputting decoded data corresponding to a current image to be displayed, the current image being stored in the main memory;
a microprocessor system coupled to the main memory, the microprocessor system storing non-image data in and retrieving data from the main memory; and
an arbiter circuit coupled to both the microprocessor system and the decoder for controlling the access to said main memory by the decoder and the microprocessor.