US 7,321,965 B2
Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
Kevin D Kissell, Le Bar sur Loup (France)
Assigned to MIPS Technologies, Inc., Mountain View, Calif. (US)
Filed on Aug. 27, 2004, as Appl. No. 10/929,342.
Application 10/929342 is a continuation in part of application No. 10/684350, filed on Oct. 10, 2003.
Application 10/684350 is a continuation in part of application No. 10/684348, filed on Oct. 10, 2003.
Claims priority of provisional application 60/502359, filed on Sep. 12, 2003.
Claims priority of provisional application 60/502358, filed on Sep. 12, 2003.
Claims priority of provisional application 60/499180, filed on Aug. 28, 2003.
Prior Publication US 2005/0125795 A1, Jun. 09, 2005
Int. Cl. G06F 9/44 (2006.01)
U.S. Cl. 712—229 82 Claims
OG exemplary drawing
 
1. A microprocessor having an instruction set in its architecture, the microprocessor comprising:
a core, configured to concurrently execute instructions of a plurality of program threads;
a yield instruction, included in the instruction set of the microprocessor, comprising:
an opcode, for instructing the microprocessor core to suspend issuing instructions of a thread, wherein said thread is one of said plurality of concurrently executed program threads, wherein the yield instruction is an instruction in said thread;
a first operand, wherein if said first operand is a first predetermined value the microprocessor core terminates issuing instructions of said thread, wherein if said first operand is a second predetermined value the microprocessor core unconditionally reschedules issuing instructions of said thread; and
a second operand, for receiving a result value of the instruction usable by other instructions of the program thread.