US 7,321,244 B2 | ||
Clock switching device and clock switching method | ||
Naoki Kobayashi, Tokyo (Japan) | ||
Assigned to NEC Corporation, Tokyo (Japan) | ||
Filed on Mar. 29, 2006, as Appl. No. 11/391,341. | ||
Claims priority of application No. 2005-100150 (JP), filed on Mar. 30, 2005. | ||
Prior Publication US 2006/0221070 A1, Oct. 05, 2006 | ||
Int. Cl. H03K 17/00 (2006.01); G06F 1/08 (2006.01) |
U.S. Cl. 327—99 [327/294; 327/298; 327/407] | 6 Claims |
4. A clock switching method of switching a clock to be supplied to an information processing device, comprising the step of:
detecting, out of a plurality of clock pulses applied, abnormality in a waveform of one of said plurality of clock pulses
applied that is being output, and switching to and outputting other clock pulse whose phase is matched with a phase of one
of said plurality of clock pulses applied that is being output;
detecting lack of coincidence in a logical level between a current clock pulse and a one-cycle preceding clock pulse as abnormality
in a waveform on the basis of said plurality of clock pulses;
adjusting the phase of said other clock pulse to the phase of said clock pulse being output;
switching to and outputting said other clock pulse whose phase is adjusted by a phase adjustment unit for switching based
on detection of lack of coincidence in said logical level;
matching a phase of a current clock pulse and a phase of a one-cycle preceding clock pulse on the basis of said plurality
of clock pulses.
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