US 7,321,285 B2
Method for fabricating a transformer integrated with a semiconductor structure
Cheng-Chou Hung, Chang-Hua Hsien (Taiwan); Hua-Chou Tseng, Hsin-Chu (Taiwan); Victor-Chiang Liang, Hsin-Chu (Taiwan); Yu-Chia Chen, Taipei (Taiwan); and Tsun-Lai Hsu, Hsin-Chu Hsien (Taiwan)
Assigned to United Microelectronics Corp., Hsin-Chu (Taiwan)
Filed on Apr. 17, 2007, as Appl. No. 11/736,565.
Application 11/736565 is a division of application No. 11/278952, filed on Apr. 06, 2006.
Prior Publication US 2007/0236320 A1, Oct. 11, 2007
Int. Cl. H01F 5/00 (2006.01)
U.S. Cl. 336—200 13 Claims
OG exemplary drawing
 
1. A transformer integrated with a semiconductor structure comprising:
a substrate;
a primary winding layer and a top interconnection metal layer formed on the substrate;
a passivation layer formed on the primary winding layer and the top interconnection metal layer, and the passivation layer having a plurality of openings exposing parts of the top interconnection metal layer; and
a secondary winding layer and at least a bonding pad respectively formed on the passivation layer and the top interconnection metal layer, and the bonding pad being electrically connected to the top interconnection metal layer through the openings;
wherein the primary winding layer and the secondary winding layer construct the transformer.