US 7,321,524 B2
Memory controller with staggered request signal output
Ian P. Shaeffer, San Jose, Calif. (US); Bret Stott, Menlo Park, Calif. (US); and Benedict C. Lau, San Jose, Calif. (US)
Assigned to Rambus Inc., Los Altos, Calif. (US)
Filed on Oct. 17, 2005, as Appl. No. 11/252,957.
Prior Publication US 2007/0086268 A1, Apr. 19, 2007
Int. Cl. G11C 8/00 (2006.01)
U.S. Cl. 365—233  [365/191; 365/194; 365/201; 365/230.08] 14 Claims
OG exemplary drawing
 
1. A memory controller comprising:
storage circuitry to store a first programmed value and a second programmed value;
a first timing signal generator to generate a first timing signal having a phase offset relative to a first clock signal in accordance with the first programmed value;
a second timing signal generator to generate a second timing signal having a phase offset relative to the first clock signal in accordance with the second programmed value; and
output driver circuitry to output, from the memory controller, an address value in response to the first timing signal and a control value in response to the second timing signal, the address value and control value constituting portions of a first memory access request.