US 7,321,979 B2 | ||
Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth | ||
Van Hoa Lee, Cedar Park, Tex. (US) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Jan. 22, 2004, as Appl. No. 10/763,077. | ||
Prior Publication US 2005/0166073 A1, Jul. 28, 2005 | ||
Int. Cl. G06F 1/04 (2006.01) |
U.S. Cl. 713—600 [713/100] | 23 Claims |
1. A method in a multi-processor data processing system, having at least one master processor, at least one slave processor,
memory, and a system core logic used to interface the processors to the memory, for changing an operating frequency of the
system core logic, the method comprising:
determining whether the operating frequency of the system core logic should be changed from a first frequency to a second
frequency;
responsive to determining the operating frequency should be changed, placing the at least one slave processor into a non-transactional
mode; and
responsive to placing the at least one slave processor into the non-transactional mode, changing the operating frequency of
the system core logic to the second frequency.
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