US 7,321,252 B2 | ||
Semiconductor integrated circuit | ||
Hiroyuki Mizuno, Kokubunji (Japan); Koichiro Ishibashi, Warabi (Japan); Takanori Shimura, Chiba (Japan); and Toshihiro Hattori, Kodaira (Japan) | ||
Assigned to Renesas Technology Corporation, Tokyo (Japan) | ||
Filed on Apr. 04, 2006, as Appl. No. 11/396,543. | ||
Application 11/396543 is a continuation of application No. 11/144695, filed on Jun. 06, 2005, granted, now 7,046,075. | ||
Application 11/144695 is a continuation of application No. 10/765923, filed on Jan. 29, 2004, granted, now 6,987,415. | ||
Application 10/765923 is a continuation of application No. 10/443018, filed on May 22, 2003, granted, now 6,707,334. | ||
Application 10/443018 is a continuation of application No. 10/247525, filed on Sep. 20, 2002, granted, now 6,600,360. | ||
Application 10/247525 is a continuation of application No. 09/582485, filed on Jun. 23, 2000, granted, now 6,483,374. | ||
Claims priority of application No. PCT/JP97/04253 (WO), filed on Nov. 21, 1997; application No. 9-359271 (JP), filed on Dec. 26, 1997; and application No. PCT/JP98/05770 (WO), filed on Dec. 21, 1998. | ||
Prior Publication US 2006/0176101 A1, Aug. 10, 2006 | ||
Int. Cl. H03L 5/00 (2006.01) |
U.S. Cl. 327—333 | 7 Claims |
1. A semiconductor integrated circuit device comprising:
an I/O circuit; and
a logic circuit comprising at least one first MOSFET of a first conductivity type on a first well area of a second conductivity
type;
wherein the I/O circuit input and output signals to and from the semiconductor integrated circuit device are via a terminal
PAD;
wherein the I/O circuit comprises a level converter used to convert a second voltage amplitude to a first voltage amplitude;
wherein at least one second MOSFET between the level converter and the terminal pad in the I/O circuit is driven by the first
voltage;
wherein the first voltage is supplied to the first well area as substrate voltage and the second voltage is supplied to the
first MOSFET as operation voltage while the logic circuit is in standby state; and
wherein the absolute value of the first voltage is higher than that of the second voltage.
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