US 7,320,924 B2 | ||
Method of producing a chip-type solid electrolytic capacitor | ||
Fumio Kida, Toyama (Japan); and Makoto Nakano, Toyama (Japan) | ||
Assigned to NEC TOKIN Corporation, Sendai-shi (Japan); and NEC TOKIN Toyama, Ltd., Toyama (Japan) | ||
Filed on Sep. 19, 2006, as Appl. No. 11/523,417. | ||
Application 11/523417 is a division of application No. 10/866154, filed on Jun. 10, 2004, granted, now 7,138,713. | ||
Claims priority of application No. 2003-170428 (JP), filed on Jun. 16, 2003. | ||
Prior Publication US 2007/0020843 A1, Jan. 25, 2007 | ||
Int. Cl. H01L 21/20 (2006.01) |
U.S. Cl. 438—396 [438/381; 438/397; 438/398; 257/E21.008; 257/E21.011; 257/E21.017] | 4 Claims |
1. A method of producing a chip-type solid electrolytic capacitor, comprising:
producing a plurality of capacitor elements, each one of the capacitor elements being produced by: (i) obtaining an anode
member by sintering a valve metal such that an anode lead is connected to the anode member, (ii) forming a dielectric oxide
layer on the anode member, and (iii) forming a cathode layer on the dielectric oxide layer;
laminating the plurality of capacitor elements with at least one cathode terminal positioned between two capacitor elements
such that the cathode layers of the two capacitor elements face each other via the cathode terminal, said cathode terminal
having at least one of a through hole and a cutout formed therein;
filling a bonding agent at an interface between each of the cathode layers and the cathode terminal and in said at least one
of the through hole and the cutout, so as to bond the capacitor elements together; and
electrically connecting the capacitor elements in parallel.
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