US 7,321,273 B2
Off-chip LC circuit for lowest ground and VDD impedance for power amplifier
Jesus Alfonso Castaneda, Los Angeles, Calif. (US); and Qiang (Tom) Li, Irvine, Calif. (US)
Assigned to Broadcom Corporation, Irvine, Calif. (US)
Filed on Oct. 09, 2006, as Appl. No. 11/539,674.
Application 11/539674 is a continuation of application No. 10/844237, filed on May 12, 2004, granted, now 7,119,631, filed on Oct. 10, 2006.
Claims priority of provisional application 60/552759, filed on Mar. 12, 2004.
Prior Publication US 2007/0080736 A1, Apr. 12, 2007
Int. Cl. H03F 3/191 (2006.01)
U.S. Cl. 333—24R  [330/302; 330/305] 19 Claims
OG exemplary drawing
 
1. An off chip LC (inductance-capacitance) circuit providing a lowest ground and VDD impedance for an on-chip power amplifier (PA), the circuit comprises:
a first radio frequency (RF) choke that couples an off chip supply potential node to a first pin of an integrated circuit;
wherein the first pin connects to an on-chip supply potential node of a die that is implemented within the integrated circuit, the on-chip supply potential node powers the on-chip PA (Power Amplifier);
a second RF choke that couples an off chip ground potential node to a second pin of the integrated circuit;
wherein the second pin connects to an on-chip ground potential node of the die, the on-chip ground potential node serves as an on-chip ground reference of the on-chip PA;
an off chip joining capacitor that couples the first pin and the second pin of the integrated circuit; and
an off chip tuning capacitor that couples the first pin of the integrated circuit and to an off chip true ground potential node.