US 7,321,512 B2
Ramp generator and relative row decoder for flash memory device
Daniele Vimercati, Carate Brianza (Italy); Marco Onorato, Concorezzo (Italy); Carmela Albano, Sant'Agata li Battiati (Italy); and Mounia El-Moutaouakil, Andalo Valtellino (Italy)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (Italy)
Filed on May 03, 2006, as Appl. No. 11/381,426.
Claims priority of application No. VA2005A0028 (IT), filed on May 03, 2005.
Prior Publication US 2006/0250852 A1, Nov. 09, 2006
Int. Cl. G11C 11/34 (2006.01)
U.S. Cl. 365—185.19  [365/185.21] 20 Claims
OG exemplary drawing
 
7. A memory device comprising:
an array of memory cells organized into a plurality of array sectors, each array sector singularly addressable through an array wordline;
at least one array of reference cells addressable through a reference wordline;
a respective voltage ramp generator for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein;
a respective row decoding circuit coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline;
a current generator for generating a current to be injected on a circuit node in a selected array sector and on a circuit node of said at least one array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp; and
a respective local ramp generating circuit for each array sector and for said at least one array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.