US 7,321,948 B1
Highly available system test mechanism
Douglas Sullivan, Hopkinton, Mass. (US); and Brandon Barney, Hudson, Mass. (US)
Assigned to EMC Corporation, Hopkinton, Mass. (US)
Filed on Mar. 30, 2005, as Appl. No. 11/94,050.
Int. Cl. G06F 13/14 (2006.01); G06F 11/00 (2006.01)
U.S. Cl. 710—305  [714/709] 20 Claims
OG exemplary drawing
 
1. Apparatus in a system comprising:
a plurality of boards;
a first set of identifying signals for identifying a first board of the plurality of boards, the first set of identifying signals capable of encoding a first valid state and one or more invalid states; and
a second set of identifying signals for identifying a second board of the plurality of boards, the second set of identifying signals capable of encoding a second valid state and one or more invalid states;
wherein if a fault occurs on any one identifying signal of the first set of identifying signals, an invalid state will be detected by the system, but the first board will remain properly identified;
wherein the first set of identifying signals are binary identifying signals and the second set of identifying signals are binary signals; and
wherein the fault is a stuck-bit fault.