US 7,321,519 B2 | ||
Adaptive algorithm for MRAM manufacturing | ||
Hsu Kai Yang, Pleasanton, Calif. (US); Xi Zeng Shi, Fremont, Calif. (US); Po-Kang Wang, San Jose, Calif. (US); and Bruce Yang, Pleasanton, Calif. (US) | ||
Assigned to Headway Technologies, Inc., Milpitas, Calif. (US); and Applied Spintronill, Inc., Milpitas, Calif. (US) | ||
Filed on Jul. 12, 2006, as Appl. No. 11/485,195. | ||
Application 11/485195 is a division of application No. 10/889911, filed on Jul. 13, 2004, granted, now 7,085,183. | ||
Prior Publication US 2006/0250865 A1, Nov. 09, 2006 | ||
Int. Cl. G11C 7/00 (2006.01) |
U.S. Cl. 365—201 [365/154; 365/158; 365/185.08; 365/189.07] | 6 Claims |
1. A method of adaptively programming, testing, and sorting magnetic random access memory array without on-chip algorithm
generator but using an external tester comprising the steps of:
a: programming & testing said memory array,
b: signalling a good SRAM die if said programming & testing said memory array indicates a good die and branching to ‘g’,
c: signaling a Fail if said programming and testing said memory array indicates a bad die,
d: programming and testing said memory array for one time write,
e: signalling a good one time programmed EPRom die if said programming and testing said memory array for one time write indicates
a pass, followed by branching to ‘g’,
f: signalling a Bad Die if said programming & testing said memory array for one time write indicates a Fail,
g: signalling process complete.
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