US 7,320,913 B2
Methods of forming split-gate non-volatile memory devices
Sung-Taeg Kang, Seoul (Korea, Republic of); Hyok-Ki Kwon, Yongin (Korea, Republic of); Bo Young Seo, Anyang-si (Korea, Republic of); Seung Beom Yoon, Suwon (Korea, Republic of); Hee Seog Jeon, Hwasung (Korea, Republic of); Yong-Suk Choi, Hwaseong (Korea, Republic of); and Jeong-Uk Han, Suwon (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (Korea, Republic of)
Filed on Mar. 03, 2006, as Appl. No. 11/368,247.
Claims priority of application No. 10-2005-0018771 (KR), filed on Mar. 07, 2005.
Prior Publication US 2006/0199336 A1, Sep. 07, 2006
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—257  [438/261; 438/267; 438/593; 438/596] 7 Claims
OG exemplary drawing
 
1. A method for fabricating a split-gate memory cell array, comprising:
forming a floating gate electrode on a semiconductor substrate;
forming a first conformal dielectric layer on the floating gate electrode and semiconductor substrate;
forming a first diffusion region in the semiconductor substrate adjacent a first side of the floating gate electrode, wherein the first diffusion region is formed such that a first side of the floating gate electrode overlaps the first diffusion region;
removing a portion of the first conformal dielectric layer that is disposed on the first side of the floating gate electrode and the first diffusion region;
forming a second conformal dielectric layer on the floating gate electrode and semiconductor substrate;
forming a conformal conductive layer over the second conformal dielectric layer on the semiconductor substrate; and
patterning the conformal conductive layer to form a coupling gate electrode on the first side of the floating gate electrode and to form a control gate electrode on a second side of the floating gate electrode; and
forming a second diffusion region in the semiconductor substrate adjacent the control gate electrode.