US 7,320,923 B2 | ||
SRAM cell | ||
Bertrand Borot, Cheylas (France); and Philippe Coronel, Barraux (France) | ||
Assigned to STMicroelectronics Crolles 2 SAS, Crolles (France) | ||
Filed on Dec. 16, 2005, as Appl. No. 11/305,553. | ||
Claims priority of application No. 04 53012 (FR), filed on Dec. 16, 2004. | ||
Prior Publication US 2006/0134876 A1, Jun. 22, 2006 | ||
Int. Cl. H01L 21/331 (2006.01) |
U.S. Cl. 438—381 [438/382; 438/393; 438/226; 257/393; 257/E27.101; 257/E27.098] | 15 Claims |
1. A method for forming a resistor of high value in a semiconductor substrate comprising the steps of:
forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer,
the third insulating layer being selectively etchable with respect to the second insulating layer;
etching the stack to expose the substrate and to retain portions of the stack along a line on the substrate;
forming insulating spacers on lateral walls of the line;
performing an epitaxial growth of a single-crystal semiconductor on the lateral walls of the line;
selectively removing the third insulating layer to form a cavity that partially exposes the second insulating layer at a predetermined
location on the line; and
depositing and etching a conductive material into the cavity.
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