US 7,321,980 B2
Software power control of circuit modules in a shared and distributed DMA system
Subrangshu Kumar Das, West Bengal (India); Ashutosh Tiwari, Chattisgargh (India); Subash Chandar Govindarajan, Tamil Nadu (India); and Karthikeyan Rajan Madathil, Bangalore (India)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on Jan. 13, 2005, as Appl. No. 11/35,216.
Claims priority of provisional application 60/536200, filed on Jan. 13, 2004.
Prior Publication US 2005/0180233 A1, Aug. 18, 2005
Int. Cl. G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 5/06 (2006.01)
U.S. Cl. 713—601  [713/600; 365/202] 6 Claims
OG exemplary drawing
 
1. A system-on-chip integrated circuit comprising:
at least one digital module having a clock signal input, at least one of said at least one digital module including an acknowledge output supplying an acknowledge output in response to a received command;
a clock circuit producing a corresponding clock signal for each of said at least one digital module;
a peripheral enable register having a bit corresponding to each of said at least one digital module, each bit storing either a first digital state indicating a power-up state for the corresponding digital module or a second opposite digital state indicating a power-down state for the corresponding digital module;
a clock gating circuit corresponding to each of said at least one digital module, each clock gating circuit connected to said clock circuit and receiving said corresponding clock signal and connected to said bit of said peripheral enable register, said clock gating circuit supplying said corresponding clock signal to said clock input of said digital module if said corresponding bit of said peripheral enable register indicates said power-up state and not supplying said corresponding clock signal to said clock input of said digital module if said corresponding bit of said peripheral enable register indicates said power-down state; and
a false acknowledge circuit corresponding to each digital module supplying an acknowledge output, each false acknowledge circuit receiving said corresponding bit of said peripheral enable register, said false acknowledge circuit supplying an acknowledge signal in response to a received command if said corresponding bit of said peripheral enable register indicates said power-down state and not supplying an acknowledge signal in response to a received command if said corresponding bit of said peripheral enable register indicates said power-up state.