US 7,321,634 B2 | ||
Method and apparatus for variable sigma-delta modulation | ||
Herbert L. Ko, Mountain View, Calif. (US) | ||
Assigned to Verigy (Singapore) Pte. Ltd., Singapore (Singapore) | ||
Filed on Dec. 17, 2004, as Appl. No. 11/15,608. | ||
Prior Publication US 2006/0133517 A1, Jun. 22, 2006 | ||
Int. Cl. H04L 27/00 (2006.01) |
U.S. Cl. 375—295 | 11 Claims |
1. A sigma-delta modulation method, comprising:
partitioning a digital input signal comprising (M+L)-bit words into a less-significant bit signal and a more-significant bit
signal wherein the partitioning comprises partitioning the digital input signal into the more-significant bit signal comprising
M-bit words and the partitioning comprises partitioning the digital input signal into the less-significant bit signal comprising
L-bit words;
performing a lower-order modulation of the less-significant bit signal to generate an intermediate output signal, the intermediate
output signal comprises P-bit words, where P is less than L;
appending the intermediate output signal to the more-significant bit signal as less significant bits to form an intermediate
input signal; and
performing a higher-order modulation of the intermediate output signal using a (M+P)-bit third order delta-sigma modulator
to generate a digital output signal, the higher-order modulation of an order higher than the lower-order modulation.
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