US 7,322,001 B2
Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
David W. Boerstler, Round Rock, Tex. (US); Eskinder Hailu, Austin, Tex. (US); and Jieming Qi, Austin, Tex. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Oct. 04, 2005, as Appl. No. 11/242,677.
Prior Publication US 2007/0079197 A1, Apr. 05, 2007
Int. Cl. G01R 31/28 (2006.01); H03K 3/017 (2006.01)
U.S. Cl. 714—733  [327/175] 24 Claims
OG exemplary drawing
 
1. An integrated circuit device apparatus, comprising:
a duty cycle correction (DCC) circuit;
a DCC circuit controller coupled to the DCC circuit;
an array coupled to the DCC circuit; and
a built-in self test circuit coupled to the array and the DCC circuit controller, wherein the built-in self test circuit performs a self test on the array using a current setting of the DCC circuit, the DCC circuit controller increments a setting of the DCC circuit to a next incremental setting in response to a result from the built-in self test circuit indicating a failure of the array, wherein the DCC circuit controller sets the current setting of the DCC circuit as a DCC setting for a chip in response to a result from the built-in self test circuit indicating a pass of the array, and wherein the failure of the array is determined by data that is written to the array failing to match data read from the array.