US 7,321,144 B2 | ||
Semiconductor device employing buried insulating layer and method of fabricating the same | ||
Chang-Woo Oh, Gyeonggi-do (Korea, Republic of); Dong-Gun Park, Gyeonggi-do (Korea, Republic of); Jeong-Dong Choe, Gyeonggi-do (Korea, Republic of); and Kyoung-Hwan Yeo, Seoul (Korea, Republic of) | ||
Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
Filed on Dec. 13, 2004, as Appl. No. 11/11,258. | ||
Claims priority of application No. 10-2003-0093437 (KR), filed on Dec. 18, 2003. | ||
Prior Publication US 2005/0133881 A1, Jun. 23, 2005 | ||
Int. Cl. H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01) |
U.S. Cl. 257—296 [438/238; 257/306; 257/E27.084; 257/E27.086] | 12 Claims |
1. A semiconductor device comprising:
a lower semiconductor substrate;
an upper silicon pattern located on the lower semiconductor substrate, and the upper silicon pattern including a channel region;
a source region and a drain region spaced apart from each other by the channel region;
a gate electrode electrically insulated from the upper silicon pattern and extending across the channel region;
a bit line and a cell capacitor electrically connected to the source region and the drain region respectively; and
a buried insulating layer interposed between the drain region and the lower semiconductor substrate, the buried insulating
layer having an extension portion partially interposed between the channet region and the lower semiconductor substrate, wherein
the source region extends below a lowermost region of the buried insulating layer and contacts the lower semiconductor substrate.
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