US 7,321,398 B2
Digital windowing for video sync separation
Dwayne G. Johnson, Flamborough (Canada)
Assigned to Gennum Corporation, (Canada)
Filed on Sep. 08, 2004, as Appl. No. 10/935,874.
Claims priority of provisional application 60/502128, filed on Sep. 11, 2003.
Claims priority of provisional application 60/502028, filed on Sep. 11, 2003.
Claims priority of provisional application 60/502036, filed on Sep. 10, 2003.
Claims priority of provisional application 60/501792, filed on Sep. 10, 2003.
Prior Publication US 2005/0052576 A1, Mar. 10, 2005
Int. Cl. H04N 5/08 (2006.01); H03L 7/00 (2006.01)
U.S. Cl. 348—533  [348/536; 348/540] 20 Claims
OG exemplary drawing
 
1. A processing circuit for a sync signal, comprising:
a trial reference counter configured to receive a reference clock as a clock input and a first sync signal as a reset input and output a first count value;
a trial sync spacing register configured to store a second count value;
a trial window shaper circuit configured to receive the first count value and the second count value and generate a trial window signal when the first count value exceeds the second count value;
a confirmation counter circuit configured to receive a window clock as a clock input, generate a confirmation count based on the window clock, and generate a confirmation signal when the confirmation count exceeds a minimum value;
a reference counter configured to receive a reference clock as a clock input and an initialization signal as a reset input and output a third count value; and
a window shaper circuit configured to receive the third count value and the second count value and generate the window signal when the third count value exceeds the second count value;
wherein the window clock comprises a logic output operation based on the trial window signal and the first sync signal.