US 7,321,172 B2
Selective plating of package terminals
Dustin P. Wood, Chandler, Ariz. (US); and Debendra Mallik, Chandler, Ariz. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Sep. 14, 2005, as Appl. No. 11/227,532.
Application 11/227532 is a division of application No. 10/685171, filed on Oct. 13, 2003, granted, now 7,186,645.
Prior Publication US 2006/0006535 A1, Jan. 12, 2006
Int. Cl. H01L 23/48 (2006.01)
U.S. Cl. 257—781  [257/E23.02] 3 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a semiconductor package having a first pad and a second pad;
wherein the first pad has a first metal and a second metal deposited thereon;
wherein the second pad has the second metal but not the first metal deposited thereon;
a Ball Grid Array (BGA) interconnect coupled to the first and second pads; and
a printed circuit board (PCB) having a third pad and a fourth pad coupled to the BGA interconnect;
wherein the third pad has the first metal and the second metal deposited thereon; and
wherein the fourth pad has the second metal but not the first metal deposited thereon.