US 7,321,518 B1
Apparatus and methods for providing redundancy in integrated circuits
Joseph Huang, San Jose, Calif. (US); Chiakang Sung, Milpitas, Calif. (US); Philip Pan, Fremont, Calif. (US); and Yan Chong, Mountain View, Calif. (US)
Assigned to Altera Corporation, San Jose, Calif. (US)
Filed on Jan. 15, 2004, as Appl. No. 10/757,928.
Int. Cl. G11C 7/00 (2006.01); G11C 29/00 (2006.01); G06F 7/38 (2006.01); H03K 19/177 (2006.01)
U.S. Cl. 365—200  [365/201; 365/230.06; 326/40; 326/39] 50 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) including redundancy circuitry configured to provide redundancy by using a decoder circuitry coupled to a scan chain, wherein the decoder circuitry is configured to decode coded defect information received from a set of circuit elements to generate decoded defect information, and to provide in parallel the decoded defect information to the scan chain.