US 7,320,926 B2
Shallow trench filled with two or more dielectrics for isolation and coupling for stress control
Min-Hwa Chi, Hsin-chu (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan)
Filed on Jan. 26, 2006, as Appl. No. 11/339,874.
Application 10/936371 is a division of application No. 10/262168, filed on Oct. 01, 2002, granted, now 6,828,211.
Application 11/339874 is a continuation of application No. 10/936371, filed on Sep. 08, 2004, granted, now 7,018,886.
Prior Publication US 2006/0121394 A1, Jun. 08, 2006
Int. Cl. H01L 21/76 (2006.01); H01L 21/20 (2006.01)
U.S. Cl. 438—435  [438/386; 257/E21.54] 17 Claims
OG exemplary drawing
 
1. A method for fabricating a n+ to n+ capacitor, comprising:
providing a stop layer on a substrate;
etching a plurality of trenches through said stop layer and into said substrate;
depositing a first layer over said stop layer and filling said trenches wherein said first layer comprises a dielectric material having a first dielectric constant;
planarizing said first layer to said stop layer leaving said first layer within said trenches;
thereafter removing said first layer from a subset of said trenches;
depositing a second layer over said stop layer and within said subset of trenches, wherein said second layer comprises a dielectric material having a second dielectric constant higher than said first dielectric constant;
planarizing said second layer to said stop layer leaving said second layer within said subset of trenches; and
forming n+ junctions on either side of one of said subset of trenches, wherein said one of said subset of trenches forms a capacitor dielectric of said n+ to n+ capacitor.