US 7,320,901 B2
Fabrication method for a chip packaging structure
Wen-Yin Chang, Taipei (Taiwan)
Assigned to Taiwan Solutions Systems Corp., Hsin-Chu (Taiwan)
Filed on Oct. 31, 2005, as Appl. No. 11/261,462.
Prior Publication US 2007/0099339 A1, May 03, 2007
Int. Cl. H01L 21/50 (2006.01)
U.S. Cl. 438—106  [257/E21.499] 21 Claims
OG exemplary drawing
 
1. A fabrication method for a chip packaging structure comprising:
providing a carrier plate, wherein a conductive layer is formed on an upper surface of said carrier plate;
forming a plurality of trenches penetrating through said conductive layer by utilizing the photolithography process;
forming a first patterned photoresist layer on said upper surface and a first photoresist layer on a downward surface of said carrier plate, wherein said trenches are filled by said first patterned photoresist layer;
filling at least a metal layer on said conductive layer between said first patterned photoresist layer, wherein said metal layer includes a plurality of conductive joints;
performing a metal surface treatment on the surface of said metal layer;
removing said first patterned layer and said first photoresist layer; and
proceeding a chip packaging process.