US 7,321,516 B2 | ||
Biasing structure for accessing semiconductor memory cell storage elements | ||
Alberto Jose' Di Martino, Syracuse (Italy); Enrico Castaldo, Catania (Italy); Nicolas Demange, Maximin (France); and Daniele Salvatore Zompi, Misterbianco (Italy) | ||
Assigned to STMicroelectronics, S.r.l., (Italy) | ||
Filed on Feb. 22, 2005, as Appl. No. 11/63,651. | ||
Claims priority of application No. 04290446 (EP), filed on Feb. 19, 2004. | ||
Prior Publication US 2005/0195637 A1, Sep. 08, 2005 | ||
Int. Cl. G11C 15/00 (2006.01) |
U.S. Cl. 365—189.09 [365/189.05; 365/49] | 29 Claims |
1. A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the
memory cell storage element, comprising:
a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage
received at a control electrode of the biasing transistor, and
a biasing voltage generator for generating the biasing voltage, wherein
the biasing voltage generator includes a feedback voltage regulation structure adapted to track changes in a threshold voltage
of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element
substantially stable against operating condition changes.
|