US 7,321,250 B2 | ||
Integrated circuit device | ||
Katsumi Tokuyama, Osaka (Japan); and Takeshi Hirayama, Osaka (Japan) | ||
Assigned to Matsushita Electric Industrial Co., Ltd., Osaka (Japan) | ||
Filed on May 25, 2006, as Appl. No. 11/440,073. | ||
Claims priority of application No. 2005-154765 (JP), filed on May 27, 2005. | ||
Prior Publication US 2006/0267655 A1, Nov. 30, 2006 | ||
Int. Cl. H03H 11/26 (2006.01) |
U.S. Cl. 327—261 [327/291] | 4 Claims |
1. An integrated circuit device which includes a logic circuit operating in synchronization with an internal reference clock
and performing signal processing on a digital signal to generate multiple pieces of data, adjusts a phase of the internal
reference clock to generate an external output clock, adjusts a phase of the data generated by the logic circuit to generate
external output data, and outputs the clock and the data in parallel from a clock output terminal and data output terminals,
the integrated circuit device, comprising:
a delay adjustment circuit which is fed with the internal reference clock and adjusts a delay of the clock,
flip-flop circuits which are fed with the data generated by the logic circuit and output the data as the external output data
to the data output terminals in synchronization with a clock outputted from the delay adjustment circuit, and
an inverting circuit for inverting the clock outputted by the delay adjustment circuit and outputting the clock as the external
output clock to the clock output terminal.
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