US 7,321,139 B2
Transistor layout for standard cell with optimized mechanical stress effect
Mi-Chang Chang, Hsinchu (Taiwan); Liang-Kai Han, Hsinchu (Taiwan); Huan-Tsung Huang, Puli Township, Nantou County (Taiwan); Wen-Jya Liang, Hsin-Chu (Taiwan); and Li-Chun Tien, Tainan (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan)
Filed on May 26, 2006, as Appl. No. 11/441,557.
Prior Publication US 2007/0284618 A1, Dec. 13, 2007
Int. Cl. H01L 27/10 (2006.01); H01L 29/739 (2006.01); H01L 29/73 (2006.01); H01L 29/74 (2006.01); H01L 31/062 (2006.01)
U.S. Cl. 257—202  [257/203; 257/204; 257/205; 257/206; 257/207; 257/208; 257/209; 257/210; 257/211; 257/401] 14 Claims
OG exemplary drawing
 
1. A layout for a transistor of a standard cell comprising:
an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and
at least one gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region,
wherein the active region is of a non-rectangular shape,
wherein a ratio of a width of the first edge to a width of the sum of the first and the second edges is at least 0.5.