US 7,320,921 B2
Smart grading implant with diffusion retarding implant for making integrated circuit chips
Chih-Hao Wang, Hsin-Chu (Taiwan); and Ta-Wei Wang, Taipei (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan)
Filed on Mar. 22, 2005, as Appl. No. 11/86,498.
Prior Publication US 2006/0216900 A1, Sep. 28, 2006
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—306  [438/162; 257/E21.343] 17 Claims
OG exemplary drawing
 
1. A method of making an integrated circuit chip, comprising:
following spacer formation, performing a relatively high-energy low-dose implant of ions into a source/drain region of a substrate;
after performing the high-energy low-dose implant, performing a diffusion retarding implant into the source/drain region of the substrate; and
after performing the high-energy low-dose implant and the diffusion retarding implant, performing a relatively low-energy high-dose implant of ions into the source/drain region of the substrate.