US 7,321,511 B2 | ||
Semiconductor device and method for controlling operation thereof | ||
Masaru Yano, Kawasaki (Japan); Hideki Arakawa, Kawasaki (Japan); and Hidehiko Shiraiwa, San Jose, Calif. (US) | ||
Assigned to Spansion LLC, Sunnyvale, Calif. (US) | ||
Filed on Dec. 22, 2005, as Appl. No. 11/316,800. | ||
Application 11/316800 is a continuation of application No. PCT/JP2004/019645, filed on Dec. 28, 2004. | ||
Prior Publication US 2006/0256617 A1, Nov. 16, 2006 | ||
Int. Cl. G11C 16/04 (2006.01); H01L 29/788 (2006.01) |
U.S. Cl. 365—185.13 [365/185.14; 257/315; 257/320] | 20 Claims |
1. A semiconductor device comprising:
a semiconductor substrate;
word lines;
global bit lines;
inversion gates formed on the semiconductor substrate, wherein the inversion gates form inversion layers serving as local
bit lines in the semiconductor substrate, the inversion layers being electrically connected to the global bit lines;
an oxide-nitride-oxide (ONO) layer overlying the inversion gates and the semiconductor substrate, wherein a nitride layer
of the ONO layer is an insulating layer; and
a memory cell formed between adjacent inversion gates and using the inversion layers as a source and a drain, the memory cell
storing two bits, one bit stored on either side of a portion of the nitride layer that is interposed between adjacent inversion
gates.
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