US 7,321,247 B2
Timer facility for high frequency processors with minimum dependency of processor frequency modes
Rolf Hilgendorf, Boeblingen (Germany); Cedric Lichtenau, Boeblingen (Germany); and Michael Fan Wang, Austin, Tex. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Aug. 26, 2004, as Appl. No. 10/926,582.
Prior Publication US 2006/0044944 A1, Mar. 02, 2006
Int. Cl. H03K 19/00 (2006.01)
U.S. Cl. 327—141  [327/160] 13 Claims
OG exemplary drawing
 
1. An apparatus for keeping time in a clock domain, comprising:
free-running clock logic that is at least configured to provide a first tic signal, and comprising free-running clock control logic;
wherein the free-running clock control logic is at least configured to decompose the first tic signal into a plurality of slower tic signals; and
time base logic that is at least configured to receive each of the plurality of slower tic signals through an associated communication channel, the time base logic comprising:
at least one adder with a number of input channels equal to a number of the plurality of slower tic signals and configured to receive the plurality of slower tic signals; and
at least one time base adder coupled to the at least one adder.