US 7,321,237 B2
Non-volatile look-up table for an FPGA
John McCollum, Saratoga, Calif. (US); Gregory Bakker, San Jose, Calif. (US); and Jonathan Greene, Palo Alto, Calif. (US)
Assigned to Actel Corporation, Mountain View, Calif. (US)
Filed on Oct. 23, 2006, as Appl. No. 11/551,973.
Application 11/551973 is a continuation of application No. 11/026336, filed on Dec. 29, 2004, granted, now 7,129,748.
Prior Publication US 2007/0047330 A1, Mar. 01, 2007
Int. Cl. G06F 7/38 (2006.01); H03K 19/173 (2006.01)
U.S. Cl. 326—37  [326/38; 326/49] 16 Claims
OG exemplary drawing
 
1. A non-volatile-memory-transistor based lookup table for an FPGA including:
a multiplexer having a plurality of address inputs, a plurality of data inputs, and an output;
a pair of series-connected non-volatile memory transistors coupled to each of the data inputs of the multiplexer; and
a sense amplifier is coupled to the output of the multiplexer.