US 7,321,369 B2 | ||
Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device | ||
David A. Wyatt, San Jose, Calif. (US); and Aditya Sreenivas, El Dorado Hills, Calif. (US) | ||
Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
Filed on Aug. 30, 2002, as Appl. No. 10/232,285. | ||
Prior Publication US 2004/0041814 A1, Mar. 04, 2004 | ||
Int. Cl. G09G 5/36 (2006.01); G06F 1/00 (2006.01) |
U.S. Cl. 345—556 [345/558; 345/522] | 24 Claims |
1. An apparatus comprising:
a plurality of queues, each queue to store commands;
a command parser coupled to the plurality of queues to fetch and process the commands stored in the plurality of queues; and
a condition code register coupled to the plurality of queues and to the command parser, the condition code register to store
a range of event conditions indicated by at least one condition code bit, and upon receipt of a wait-on-event command, to
instruct the command parser to at least partially suspend command processing until a specified condition occurs, wherein the
wait-on-event command comprises:
at least one mask bit to indicate which bits of the condition code register are to be overwritten; and
at least one condition code bit to be written into the condition code register as dictated by the mask bits, the condition
code bit to indicate the specified condition that will allow the command parser to resume command processing.
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