US 7,321,950 B2
Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
Mark David Bellows, Rochester, Minn. (US); Paul Allen Ganfield, Rochester, Minn. (US); Kent Harold Haselhorst, Byron, Minn. (US); Ryan Abel Heckendorf, Rochester, Minn. (US); and Tolga Ozguner, Rochester, Minn. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Feb. 03, 2005, as Appl. No. 11/50,021.
Prior Publication US 2006/0174082 A1, Aug. 03, 2006
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—5  [711/154; 711/168] 14 Claims
OG exemplary drawing
 
1. A system comprising:
a memory controller with logic effective to:
provide a write operation that corresponds to a first memory bank set that is included in a memory;
identify a command cycle to allow a read operation that corresponds to a second memory bank set, the first memory bank set different than the second memory bank set;
issue the read operation based upon the identifying; and
wherein the logic includes one or more in-use counters, the logic further effective to:
load an in-use counter value into one of the in-use counters;
adjust the in-use counter value;
determine whether the in-use counter value has reached a predetermined number in response to the adjusting;
allow a same bank set read operation based upon determining that the in-use counter value has reached the predetermined number; and
reset an unavailable counter in response to determining that the in-use counter value has reached the predetermined number.