US 7,320,931 B2
Interfacial layer for use with high k dielectric materials
Shawn G. Thomas, Gilbert, Ariz. (US); Vida Ilderem, Phoenix, Ariz. (US); and Papu D. Maniar, Mesa, Ariz. (US)
Assigned to Freescale Semiconductor Inc., Austin, Tex. (US)
Filed on Jul. 30, 2004, as Appl. No. 10/903,841.
Prior Publication US 2006/0022283 A1, Feb. 02, 2006
Int. Cl. H01L 29/72 (2006.01)
U.S. Cl. 438—503  [438/471; 438/478; 438/585; 257/310; 257/407; 257/410; 257/532; 257/616] 18 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure comprising the steps of:
providing a silicon substrate with an exposed surface;
inhibiting formation of one or more oxides on the exposed surface of the silicon substrate, wherein inhibiting comprises the steps of:
cleaning the exposed surface of the silicon substrate to reduce the presence of oxides;
depositing a layer of substantially pure germanium directly on the cleaned, exposed surface of the silicon substrate such that the germanium layer is less than approximately 14 Å in thickness and is epitaxially matched to the silicon substrate, wherein the deposited substantially pure germanium layer has an exposed surface; and
cleaning the exposed surface of the substantially pure germanium layer to reduce the presence of oxides; and
forming a dielectric layer of high k material directly on the cleaned, exposed surface of the substantially pure germanium layer.