US 7,320,918 B2
Method and structure for buried circuits and devices
John E. Campbell, Wappingers Falls, N.Y. (US); William T. Devine, Ulster Park, N.Y. (US); and Kris V. Srikrishnan, Wappingers Falls, N.Y. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on May 11, 2005, as Appl. No. 11/126,675.
Application 11/126675 is a division of application No. 10/832894, filed on Apr. 27, 2004, granted, now 7,141,853.
Application 10/832894 is a division of application No. 09/879530, filed on Jun. 12, 2001, granted, now 6,759,282.
Prior Publication US 2005/0214988 A1, Sep. 29, 2005
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—279  [257/E21.412] 17 Claims
OG exemplary drawing
 
1. A method of fabricating a circuit provided on a semiconductor-on-insulator (SOI) substrate, the method comprising:
forming a plurality of field effect transistors (FETs), including a first FET and a second FET disposed in a common device layer, the first FET having a gate disposed below the common device layer, the second FET having a gate disposed above the common device layer, the first and second FETs sharing a common body layer, a third and fourth FET, the third FET having a gate disposed below the common device layer, the fourth FET having a gate disposed above the common device layer, the third and fourth FETs sharing a common body layer, the first and second FETs being interconnected in series by a first source/drain region, the second and third FETs being interconnected in series by a second source/drain region, the third and fourth FETs being interconnected in series by a third source/drain region, a gate electrode of the first FET and a gate electrode of the third FET being coupled to a first conductor for providing a first clock signal, a gate electrode of the second FET and a gate electrode of the fourth FET being coupled to a second conductor for providing a second clock signal, wherein the circuit includes a dynamic two-phase shift register.