US 7,322,015 B2
Simulating a dose rate event in a circuit design
Harry H. L. Liu, Plymouth, Minn. (US); Keith W. Golke, Minneapolis, Minn. (US); Eric E. Vogt, Minneapolis, Minn. (US); and Michael S. Liu, Bloomington, Minn. (US)
Assigned to Honeywell Internatinal Inc., Morristown, N.J. (US)
Filed on Jan. 05, 2005, as Appl. No. 11/29,308.
Prior Publication US 2006/0145086 A1, Jul. 06, 2006
Int. Cl. G06F 17/50 (2006.01); G06G 7/62 (2006.01)
U.S. Cl. 716—4  [703/14] 23 Claims
OG exemplary drawing
 
1. A method of using a subcircuit model for dose rate simulation of a circuit design, comprising in combination:
replacing an NMOS transistor in a circuit design with a subcircuit model, wherein the subcircuit model includes:
an NMOS transistor having a source, a drain, a body, and a gate;
a first diode having an anode connected to the body and a cathode connected to the drain;
a first current source connected in parallel with the first diode, wherein current flows through the first current source from the drain to the body, and wherein the first diode and the first current source provide a model of a drain junction during a dose rate event;
a second diode having an anode connected to the body and a cathode connected to the source;
a second current source connected in parallel with the second diode, wherein current flows through the second current source from the source to the body, and wherein the second diode and the second current source provide a model of a source junction during the dose rate event;
an NMOS transistor size parameter;
a dose rate parameter of the dose rate event; and
performing a computer simulation of the circuit design to determine dose rate hardness of the circuit design.