US 7,321,171 B2
Semiconductor integrated circuit device
Tatsuyuki Saito, Ome (Japan); Naohumi Ohashi, Hanno (Japan); Toshinori Imai, Ome (Japan); Junji Noguchi, Ome (Japan); and Tsuyoshi Tamaru, Hachiouji (Japan)
Assigned to Renesas Technology Corp., Tokyo (Japan)
Filed on Oct. 22, 2004, as Appl. No. 10/970,024.
Application 10/970024 is a division of application No. 09/850162, filed on May 08, 2001, granted, now 6,818,546.
Claims priority of application No. 2000-135041 (JP), filed on May 08, 2000.
Prior Publication US 2005/0095844 A1, May 05, 2005
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01)
U.S. Cl. 257—774  [257/750; 257/751; 257/758] 18 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device, comprising a first insulating film formed on a semiconductor substrate, a groove for wiring formed in said first insulating film, a barrier layer formed at side walls and a bottom of said groove for wiring, a conductive film formed inside said groove for wiring and formed on said barrier layer, a cap conductive film formed on said conductive film, and a second insulating film formed on said cap conductive film and said first insulating film,
wherein said first insulating film has an outer main surface that is at a lower plane than an outer main surface of said cap conductive film.