US 7,321,149 B2 | ||
Capacitor structures, and DRAM arrays | ||
Brett W. Busch, Boise, Id. (US); Luan C. Tran, Meridian, Id. (US); Ardavan Niroomand, Boise, Id. (US); Fred D. Fishburn, Boise, Id. (US); and Richard D. Holscher, Boise, Id. (US) | ||
Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
Filed on Jul. 22, 2005, as Appl. No. 11/187,210. | ||
Application 11/187210 is a division of application No. 10/783843, filed on Feb. 20, 2004, granted, now 7,153,778. | ||
Prior Publication US 2005/0269620 A1, Dec. 08, 2005 | ||
Int. Cl. H01L 29/72 (2006.01) |
U.S. Cl. 257—306 [257/301; 257/303; 257/516; 257/532; 257/E27.048; 257/E27.071; 257/E27.092] | 7 Claims |
1. A capacitor structure, comprising:
a semiconductor substrate;
an insulative material over the semiconductor substrate;
a container opening extending into the insulative material, the container opening having a vertical dimension corresponding
to a depth of the opening and a horizontal dimension orthogonal to the vertical dimension, and comprising a substantially
five-sided cross-section along the horizontal dimension; and
a first capacitor electrode, a dielectric material and a second capacitor electrode extending within the container opening.
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