US 7,321,514 B2
DRAM memory cell arrangement
Ulrike Gruening-von Schwerin, Munich (Germany)
Assigned to Infineon Technologies AG, Munich (Germany)
Filed on Apr. 29, 2005, as Appl. No. 11/117,853.
Claims priority of application No. 10 2004 021 051 (DE), filed on Apr. 29, 2004.
Prior Publication US 2005/0254279 A1, Nov. 17, 2005
Int. Cl. G11C 7/10 (2006.01)
U.S. Cl. 365—189.01  [365/149; 365/104] 19 Claims
OG exemplary drawing
 
1. A memory cell arrangement comprising:
a plurality of memory cells defined by a plurality of cell rows and cell columns, each cell column having a gate electrode; and
a plurality of word lines and rear side electrode lines arranged alternately between adjacent cell columns, wherein the gate electrodes of two adjacent cell columns are connected to a word line between the adjacent cell columns;
wherein the rear side electrode of adjacent cell columns are connected to a rear side line between the cell columns and the rear side line is held at a fixed potential.