US 7,321,997 B2
Memory channel self test
David Zimmerman, El Dorado Hills, Calif. (US); Edward Weaver, Sunnyvale, Calif. (US); and Ramasubramanian Rajamani, Cupertino, Calif. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Mar. 30, 2004, as Appl. No. 10/815,217.
Prior Publication US 2005/0223303 A1, Oct. 06, 2005
Int. Cl. G11C 29/00 (2006.01); G01R 31/28 (2006.01)
U.S. Cl. 714—718  [714/724] 13 Claims
OG exemplary drawing
 
1. An electronic system comprising:
a first memory module having a first memory array and a first buffer logic coupled to the first memory array;
a second memory module having a second memory array and a second buffer logic coupled to the second memory array; and
an analysis module having a third buffer logic and an analysis device coupled to the third buffer logic, wherein the analysis module is interposed between the second buffer logic and the first buffer logic,
wherein the second buffer logic transmits a test pattern through the third buffer logic to the first buffer logic to carry out a test of the first memory module independently of a memory controller, and the analysis device analyzes a result of the test transmitted by the first buffer logic.