US 7,321,155 B2
Offset spacer formation for strained channel CMOS transistor
Chih-Hsin Ko, Fongshan (Taiwan); Wen-Chin Lee, Hsin-chu (Taiwan); and Chung-Hu Ge, Taipei (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan)
Filed on May 06, 2004, as Appl. No. 10/840,911.
Prior Publication US 2005/0247986 A1, Nov. 10, 2005
Int. Cl. H01L 29/772 (2006.01)
U.S. Cl. 257—408  [257/900; 257/E29.266] 25 Claims
OG exemplary drawing
 
1. A strained channel transistor comprising:
a semiconductor substrate;
a gate dielectric overlying a channel region;
a gate electrode overlying the gate dielectric;
source/drain extension (SDE) regions and source and drain (S/D) regions;
an internally stressed pair of offset spacers disposed adjacent the sides of the gate electrode, said internal stress originating from within said offset spacers, wherein only a portion of a bottom surface portion of each of the pair of stressed offset spacers contacts the semiconductor substrate, said internal stress being compressive for a P charge mobility transistor or tensile for a N charge mobility transistor; and,
an internally stressed dielectric layer disposed over the gate electrode, the internally stressed offset spacers, and the S/D regions, said internal stress originating from within said dielectric layer;
wherein said stressed offset spacers and stressed dielectric layer are formed with a respective desired level of stress to cooperatively exert a desired strain on the channel region to improve said P or N charge mobility.