US 7,321,996 B1 | ||
Digital data error insertion methods and apparatus | ||
Andrew Draper, Chesham (United Kingdom); and Kulwinder Dhanoa, Southhall (United Kingdom) | ||
Assigned to Altera Corporation, San Jose, Calif. (US) | ||
Filed on Sep. 09, 2004, as Appl. No. 10/939,064. | ||
Int. Cl. G06F 11/00 (2006.01) |
U.S. Cl. 714—703 | 19 Claims |
8. A method for testing error correcting code circuitry, comprising:
receiving a data word to transmit to a destination;
combining the data word with another word using a logic gate, wherein the other word contains a same number of bits as the
data word and the combining comprises:
leaving the data word unaltered when each bit of the other word contains a value of zero; and
altering the data word when at least one bit of the other word contains a value of one; and
transmitting a result of the combining to the destination.
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