US 7,321,603 B1 | ||
Method and system for reducing bit error rate in a high-speed four to one time domain multiplexer | ||
Tom Peter Edward Broekaert, Calabasas, Calif. (US) | ||
Assigned to Inphi Corp., Westlake Village, Calif. (US) | ||
Filed on Apr. 03, 2002, as Appl. No. 10/115,729. | ||
Int. Cl. H04J 3/02 (2006.01) |
U.S. Cl. 370—539 [365/189.02; 365/189.05] | 18 Claims |
1. A high speed time domain four-to-one multiplexer, comprising:
a first two-to-one multiplexer having a first input for receiving a first data source, a second input for receiving a second
data source, a clock input for receiving a clock signal, and a first output, the first two-to-one multiplexer further comprising:
a first selector gate; and
a first plurality of latches disposed as a first flip-flop and a second flip-flop, wherein the first flip-flop comprises a
first latch in the first plurality of latches generating a first keep-alive current and a second latch in the first plurality
of latches comprising a second keep-alive current;
a second two-to-one multiplexer having a third input for receiving a third data source, a fourth input for receiving a fourth
data source, a second output, and a second plurality of latches, a first latch in the second plurality of latches generating
a third keep-alive current; and
a third two-to-one multiplexer having a fifth input coupled to the first output of the first two-to-one multiplexer, a sixth
input coupled to the second output of the second two-to-one multiplexer, a third output, and a third plurality of latches,
a first latch in the third plurality of latches generating a fourth keep-alive current.
|