US 7,321,249 B2 | ||
Oscillator, frequency multiplier, and test apparatus | ||
Daisuke Watanabe, Tokyo (Japan); and Toshiyuki Okayasu, Tokyo (Japan) | ||
Assigned to Advantest Corporation, Tokyo (Japan) | ||
Filed on May 26, 2006, as Appl. No. 11/441,796. | ||
Application 11/441796 is a continuation of application No. PCT/JP2004/017554, filed on Nov. 26, 2004. | ||
Claims priority of application No. 2003-399603 (JP), filed on Nov. 28, 2003. | ||
Prior Publication US 2006/0261903 A1, Nov. 23, 2006 | ||
Int. Cl. H03K 3/00 (2006.01) |
U.S. Cl. 327—251 [331/45] | 25 Claims |
1. An oscillator for generating an oscillating signal having desired frequency, comprising:
a reference oscillating section for generating a reference signal having predetermined frequency;
a plurality of first variable delay circuits, connected in cascade, for receiving said reference signal and outputting said
received reference signal by sequentially delaying by almost equal value of delay;
a phase comparing section for comparing phase of said reference signal generated by said reference oscillating section with
phase of a delay signal outputted out of a final stage of said plurality of first variable delay circuits;
a delay control section for controlling a value of delay of said plurality of first variable delay circuits so that the phase
of said reference signal becomes almost equal to the phase of the delay signal outputted out of the final stage of said plurality
of first variable delay circuits; and
a frequency adding circuit for generating said oscillating signal in which edges of said respective input signals are combined
by logically operating the input signals inputted to said respective first variable delay circuits,
wherein said oscillator generates said oscillating signal having frequency of k times (where k is an integer of 2 or more)
of frequency of said reference signal; 2k of said first variable delay circuits are connected in cascade and are provided
respectively with a value of delay almost equal to ½k times of period of said reference signal; and said frequency adding
circuit generates rising and falling edges of said oscillating signal based on rising edges of said input signals inputted
respectively to said plurality of first variable delay circuits,
further comprising:
a plurality of second variable delay circuits, connected in cascade, for receiving said delay signal outputted out of the
final stage of said plurality of first variable delay circuits and outputting said received delay signal by sequentially delaying
by almost equal values of delay with said first variable delay circuits; and
a plurality of voltage adding circuits, provided per each stage of said plurality of first variable delay circuits and said
plurality of second variable delay circuits, for adding voltage level of said input signals inputted respectively to said
first variable delay circuits and said second variable delay circuits provided in the same stage in said plurality of first
variable delay circuits and said plurality of second variable delay circuits and for supplying them to said frequency adding
circuit.
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