US 7,321,951 B2
Method for testing flash memory power loss recovery
Wanmo Wong, Menlo Park, Calif. (US); and Karunakaran Muthusamy, Fremont, Calif. (US)
Assigned to Micron Technology, Inc., Boise, Id. (US)
Filed on Nov. 17, 2003, as Appl. No. 10/714,780.
Prior Publication US 2005/0108491 A1, May 19, 2005
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—103  [711/167] 39 Claims
OG exemplary drawing
 
1. A method of operating a non-volatile memory device driver comprising:
counting a number of low level write and/or erase access cycles of a non-volatile memory command to a non-volatile memory without regard to a failure of the low level write and/or erase access cycle, wherein each low level write and/or erase access cycle modifies the state of at least one non-volatile memory cell of the non-volatile memory;
halting access to the non-volatile memory at a selected count of low level write and/or erase access cycles;
changing the selected count;
re-executing the non-volatile memory command;
counting the number of low level write and/or erase access cycles; and
halting access to the non-volatile memory at the changed count of low level write and/or erase access cycles.