US 7,320,909 B2
Methods of fabricating integrated circuit devices having contact holes exposing gate electrodes in active regions
Jeung-Hwan Park, Gyeonggi-do (Korea, Republic of); and Myoung-Kwan Cho, Gyeongsangbuk-do (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of)
Filed on Feb. 22, 2006, as Appl. No. 11/359,840.
Application 11/359840 is a division of application No. 10/769649, filed on Jan. 30, 2004, granted, now 7,034,365.
Claims priority of application No. 10-2003-006598 (KR), filed on Feb. 03, 2003.
Prior Publication US 2006/0141715 A1, Jun. 29, 2006
Int. Cl. H01L 21/337 (2006.01)
U.S. Cl. 438—195  [438/199; 438/279; 257/E21.611] 5 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device comprising:
forming an integrated circuit substrate;
forming first, second and third spaced apart insulating regions in the integrated circuit substrate that define first and second active regions;
forming a first gate electrode on the first active region, the first gate electrode having a first portion on the first active region that extends onto the first insulating region and a second portion at an end of the first portion on the first insulating region;
forming a second gate electrode on the second active region; and
forming an insulating layer on the first, second and third insulating regions defining a first gate contact hole that exposes at least a portion of the second portion of the first gate electrode, the first gate electrode being free of a gate contact hole on the first portion, and a second gate contact hole on the second active region that exposes at least a portion of the second gate electrode,
wherein the second gate electrode comprises a first portion on the second active region that extends on the third insulating region and a second portion at an end of the first portion on the third insulating region; and
wherein the second gate contact hole exposes at least a portion of the first portion of the second gate electrode, wherein forming the insulating layer further comprises forming an insulating layer that defines a third gate contact hole, and wherein the third gate contact hole exposes at least a portion of the second portion of the second gate electrode.