US 7,321,236 B2
Apparatus and methods for programmable logic devices with improved performance characteristics
Irfan Rahim, San Jose, Calif. (US); and Jeffrey T. Watt, Palo Alto, Calif. (US)
Assigned to Altera Corporation, San Jose, Calif. (US)
Filed on Feb. 07, 2007, as Appl. No. 11/672,444.
Application 11/672444 is a continuation of application No. 11/302938, filed on Dec. 14, 2005, granted, now 7,183,800.
Prior Publication US 2007/0132482 A1, Jun. 14, 2007
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/16 (2006.01)
U.S. Cl. 326—27  [327/534] 20 Claims
OG exemplary drawing
 
1. A programmable logic device (PLD), comprising a memory cell configured to provide a first voltage to a gate of a pass transistor and a second voltage to a body of the pass transistor.