US RE40,007 E1
In-situ strip process for polysilicon etching in deep sub-micron technology
Horng-Wen Chen, Hsin Chu (Taiwan); and Chi-How Wu, Tainan (Taiwan)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan)
Filed on Aug. 28, 2003, as Appl. No. 10/650,886.
Application 10/650886 is a reissue of application No. 09/669159, filed on Sep. 25, 2000, now 6,283,131, filed on Sep. 04, 2001.
Int. Cl. B08B 7/02 (2006.01); H01L 21/302 (2006.01)
U.S. Cl. 134—1.2  [430/5; 438/725; 438/719; 438/717; 438/734; 438/736; 438/739] 55 Claims
OG exemplary drawing
 
[ 20. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate with a conductive layer formed thereon;
providing a hard mask layer above said conductive layer, said hard mask layer comprising silicon oxynitride;
providing a buffer layer above said hard mask layer;
providing a resist layer above said buffer layer;
patterning said resist layer to form a resist mask that exposes a part of said buffer layer; and
patterning said conductive layer in a dry plasma etch chamber, said patterning comprising:
etching said hard mask layer and said buffer layer exposed by said resist mask to form a hard mask that exposes a part of said conductive layer;
thereafter stripping away said resist mask; and
thereafter etching said conductive layer exposed by said hard mask.]