US 7,321,957 B2
Debugging a trusted component in a system
Moinul H. Khan, Austin, Tex. (US); Mark N. Fullerton, Austin, Tex. (US); Anitha Kona, Austin, Tex. (US); and Jeffrey S. Boyer, Dripping Springs, Tex. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Oct. 24, 2003, as Appl. No. 10/693,344.
Prior Publication US 2005/0091520 A1, Apr. 28, 2005
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—152  [717/124; 713/193; 711/150] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first circuitry to permit access, responsive to entering a first password, to a first set of resources to debug a first set of code in memory;
a storage structure to contain a second password;
a second circuitry coupled to the first circuitry and to the storage structure to permit access, responsive to entering the second password, to a second set of resources to debug a second set of code in the memory; wherein said first set of resources comprises a first portion of the memory and said second set of resources comprises a second portion of the memory different than the first portion; and
circuitry to prevent the access responsive to said entering the first password if the access responsive to said entering the second password is enabled, and to prevent the access responsive to said entering the second password if the access responsive to said entering the first password is enabled.