US 7,321,142 B2
Field effect transistor
Kazuhiro Fujikawa, Osaka (Japan); Shin Harada, Osaka (Japan); Hiroyuki Matsunami, Yawata (Japan); and Tsunenobu Kimoto, Kyoto (Japan)
Assigned to Sumitomo Electric Industries, Ltd., Osaka-shi (Japan)
Appl. No. 10/544,017
PCT Filed May 21, 2004, PCT No. PCT/JP2004/007397
§ 371(c)(1), (2), (4) Date Jul. 29, 2005,
PCT Pub. No. WO2004/112150, PCT Pub. Date Dec. 23, 2004.
Claims priority of application No. 2003-169475 (JP), filed on Jun. 13, 2003.
Prior Publication US 2006/0113574 A1, Jun. 01, 2006
Int. Cl. H01L 29/80 (2006.01)
U.S. Cl. 257—256  [257/487; 257/E29.242] 4 Claims
OG exemplary drawing
 
1. A field effect transistor, comprising:
a semiconductor substrate having a main surface;
a first semiconductor layer of a first conductivity type formed on the main surface of said semiconductor substrate;
a second semiconductor layer of a second conductivity type formed on said first semiconductor layer;
a third semiconductor layer of the first conductivity type formed on said second semiconductor layer;
a pair of source and drain region layers formed in said third semiconductor layer separated by a prescribed distance from each other; and
a gate region layer formed at a part of a region of said third semiconductor layer between said pair of source and drain region layers, wherein
said first semiconductor layer includes
a buffer layer formed on a side where said third semiconductor layer is positioned and having a first impurity concentration, and
an electric field relaxation layer formed at a region between said buffer layer and said semiconductor substrate so as to contact said semiconductor substrate and having a second impurity concentration being higher than said first impurity concentration.