US 7,321,978 B2
Overclock detection
Franklin D. Brodsky, Chandler, Ariz. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Dec. 15, 2004, as Appl. No. 11/14,120.
Prior Publication US 2006/0129867 A1, Jun. 15, 2006
Int. Cl. G06F 1/08 (2006.01)
U.S. Cl. 713—500  [714/10; 714/814] 18 Claims
OG exemplary drawing
 
1. A method comprising defining a plurality of detection periods based upon a reference clock signal;
generating an operating count of an operating clock signal for each detection period of the plurality detection periods, and
determining that the operating clock signal is being overclocked in response to the operating count having a predetermined relationship to a threshold for at least a predetermined number of consecutive detection periods,
wherein defining the detection period comprises:
generating a reference count based upon the reference clock signal,
activating a detection period signal in response to the reference count having a predetermined relationship to a reference count threshold, and
generating a detection period reset signal that is synchronized to the operating clock signal.