US 7,321,648 B2 | ||
Drift compensation system and method in a clock device of an electronic circuit | ||
Lionel Guenoun, Nice (France); Denis Roman, LaTurbie (France); and Jean-Pierre Suzzoni, Cagnes sur Mer (France) | ||
Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
Filed on Jun. 30, 2004, as Appl. No. 10/710,279. | ||
Claims priority of application No. 03368079 (EP), filed on Aug. 13, 2003. | ||
Prior Publication US 2006/0002499 A1, Jan. 05, 2006 | ||
Int. Cl. H04L 7/00 (2006.01) |
U.S. Cl. 375—371 [375/376; 375/327; 375/354] | 14 Claims |
1. A drift compensation system comprising:
a first clock phase alignment circuit for providing an output clock signal which is frequency locked to an input reference
clock signal;
a second clock phase alignment circuit having input thereto the output clock signal provided by said first clock phase alignment
circuit;
a first deviation means at an output of said first clock phase alignment circuit for providing a first deviation between a
current clock phase of said first clock phase alignment circuit and an initial clock phase thereof;
a second deviation means at an output of said second clock phase alignment circuit for providing a second deviation between
a current clock phase of said second clock phase alignment circuit and an initial clock phase thereof; and
a phase control logic for providing first phase shift signals as inputs to said first clock phase alignment circuit to cancel
a phase shift between said output clock signal and said reference clock signal in response to a difference between said first
deviation and said second deviation.
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