US 7,320,164 B2
Method of manufacturing an electronic component
Hajime Yamada, Otsu (Japan); Masaki Takeuchi, Otsu (Japan); Hideki Kawamura, Shiga-ken (Japan); and Yukio Yoshino, Otsu (Japan)
Assigned to Murata Manufacturing Co., Ltd., Kyoto (Japan)
Filed on Mar. 31, 2005, as Appl. No. 11/97,888.
Application 11/097888 is a division of application No. 10/338707, filed on Jan. 09, 2003, abandoned.
Claims priority of application No. 2002-003304 (JP), filed on Jan. 10, 2002; and application No. 2002-327253 (JP), filed on Nov. 11, 2002.
Prior Publication US 2005/0168105 A1, Aug. 04, 2005
Int. Cl. H01L 41/047 (2006.01)
U.S. Cl. 29—25.35  [29/847; 310/312; 310/365] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing an electronic component, comprising the steps of:
forming a dummy electrode and a lower electrode on a substrate such that the dummy electrode is electrically connected to the lower electrode;
forming a piezoelectric thin film on the lower electrode and the dummy electrode while a predetermined bias potential is applied to the lower electrode and the dummy electrode;
removing the dummy electrode together with a peripheral portion of the piezoelectric thin film; and
forming an upper electrode on the piezoelectric thin film such that a portion of the upper electrode and a portion of the lower electrode define a pair of vertically opposing excitation electrodes with the piezoelectric thin film therebetween.