US 7,321,248 B2 | ||
Phase adjustment method and circuit for DLL-based serial data link transceivers | ||
Bo Zhang, Las Flores, Calif. (US) | ||
Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
Filed on Apr. 12, 2006, as Appl. No. 11/401,959. | ||
Application 11/401959 is a continuation of application No. 10/882428, filed on Jul. 02, 2004, granted, now 7,038,510. | ||
Prior Publication US 2006/0181319 A1, Aug. 17, 2006 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. H03L 7/06 (2006.01) |
U.S. Cl. 327—149 [327/158] | 23 Claims |
18. A delay locked loop circuit comprising:
a first flip flop configured to receive a first clock phase to sample input data at the first clock phase;
a second flip flop configured to receive a second clock phase to sample the input data at the second clock phase;
a first demultiplexer coupled to the first flip flop to produce peak data;
a second demultiplexer coupled to the second flip flop to produce zero data;
a timing recovery circuit to produce phase control signal based on the zero data and the peak data;
a first phase interpolator to adjust the first clock phase relative to the second clock phase based upon the phase control
signal; and
a second phase interpolator to adjust the second clock phase relative to the first clock phase based upon the phase control
signal.
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