US 7,322,018 B2
Method and apparatus for computing feature density of a chip layout
Keith D. Rast, Yacolt, Wash. (US); and Zia Azam, Cary, N.C. (US)
Assigned to Synopsys, Inc., Mountain View, Calif. (US)
Filed on Aug. 29, 2005, as Appl. No. 11/214,959.
Claims priority of provisional application 60/657197, filed on Feb. 28, 2005.
Prior Publication US 2006/0195803 A1, Aug. 31, 2006
Int. Cl. G06F 17/50 (2006.01)
U.S. Cl. 716—5  [716/6] 16 Claims
OG exemplary drawing
 
1. A method for computing feature density for a number of areas within a layout by moving a window across the layout, which allows the method to identify an area in the layout that violates a design rule, the method comprising:
receiving a layout;
placing the window at a first location in the layout;
computing a first feature density value based on the features within the window at the first location;
determining a second location in the layout as a function of the first location and the first feature density value;
moving the window to the second location;
computing a second feature density value based on the features within the window at the second location;
wherein determining the second location in the layout based on the first feature density value instead of using a constant displacement from the first location allows the method to accurately identify an area that violates the design rule determining whether an area violates the design rule by comparing a feature density value with the density threshold; and
flagging the area if the area violates the design rule.