US 7,320,906 B2 | ||
Thin film transistor array panel and manufacturing method thereof | ||
Min-Wook Park, Yongin-si (Korea, Republic of); Bum-Ki Baek, Suwonsi (Korea, Republic of); Jeong-Young Lee, Yongin-si (Korea, Republic of); Kwon-Young Choi, Goyang-si (Korea, Republic of); Sang-Ki Kwak, Suwon-si (Korea, Republic of); and Sang-Jin Jeon, Seoul (Korea, Republic of) | ||
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
Filed on Aug. 19, 2004, as Appl. No. 10/922,343. | ||
Claims priority of application No. 10-2003-0057295 (KR), filed on Aug. 19, 2003. | ||
Prior Publication US 2005/0110014 A1, May 26, 2005 | ||
Int. Cl. H01L 21/84 (2006.01) |
U.S. Cl. 438—158 [438/708; 438/E21.017] | 18 Claims |
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming a gate line on a substrate;
depositing a gate insulating layer and a semiconductor layer in sequence on the gate line;
depositing a first conductive layer on the semiconductor layer;
photo-etching the first conductive layer and the semiconductor layer;
depositing a passivation layer;
photo-etching the passivation layer to form contact holes and openings which expose first and second portions of the first
conductive layer;
depositing a second conductive layer; and
etching the second and the first conductive layers to simultaneously form a pixel electrode on the first portion of the first
conductive layer and to remove the second portion of the first conductive layer.
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