US 7,321,505 B2 | ||
Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect | ||
Kenji Noda, Fukuoka (Japan) | ||
Assigned to NSCore, Inc., Fukuoka (Japan) | ||
Filed on Mar. 03, 2006, as Appl. No. 11/367,952. | ||
Prior Publication US 2007/0206413 A1, Sep. 06, 2007 | ||
This patent is subject to a terminal disclaimer. | ||
Int. Cl. G11C 11/00 (2006.01) |
U.S. Cl. 365—154 [365/185.08] | 16 Claims |
1. A memory circuit, comprising:
a latch including MIS transistors, said latch having a first node and a second node configured to be bi-stable with a potential
of the first node inverse to a potential of the second node;
a plate line;
a word selecting line;
a first MIS transistor having one of source/drain nodes thereof coupled to the first node of said latch, another one of the
source/drain nodes thereof coupled to said plate line, and a gate node thereof coupled to said word selecting line;
a second MIS transistor having one of source/drain nodes thereof coupled to the second node of said latch, another one of
the source/drain nodes thereof coupled to said plate line, and a gate node thereof coupled to said word selecting line; and
a driver circuit configured to set said plate line to a first potential causing the first node to serve as a source node of
said first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node
of said first MIS transistor in a second operation mode, said first operation mode causing a lingering change in characteristics
of said first MIS transistor.
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