US 7,321,621 B2 | ||
Differential receiver circuit with electronic dispersion compensation for optical communications systems | ||
Petre Popescu, Ottawa (Canada); Douglas Stuart McPherson, Ottawa (Canada); Stefan Szilagyi, Ottawa (Canada); Quoc Hai Tran, Ottawa (Canada); and Kathryn Howlett, Ottawa (Canada) | ||
Assigned to Applied Micro Circuits Corporation, San Diego, Calif. (US) | ||
Filed on Aug. 12, 2003, as Appl. No. 10/638,340. | ||
Claims priority of provisional application 60/479459, filed on Jun. 19, 2003. | ||
Prior Publication US 2004/0258145 A1, Dec. 23, 2004 | ||
Int. Cl. H03H 7/40 (2006.01) |
U.S. Cl. 375—233 [375/316] | 21 Claims |
1. A receiver circuit, comprising:
a differential analog feed forward equalizer (FFE) circuit for receiving a dispersion distorted analog signal and processing
the received signal to generate an equalized analog data signal (dispersion compensated signal), the FFE being a finite impulse
response (FIR) filter with adjustable tap weights, the tap weights having been set to provide dispersion compensation of the
signal; and
a differential clock and data recovery (CDR) circuit for receiving the equalized analog data signal and processing the received
equalized analog data signal to generate a recovered clock signal and a retimed digital data signal, wherein the dispersion
distorted analog signal; the equalized analog data signal; a signal providing the tap weights; the recovered clock signal;
and the retimed digital data signal are differential signals;
wherein the FFE circuit comprises:
a differential tapped delay line having a delay line input, “n-1” delay elements and “n” output taps, the delay line receiving
the dispersion distorted analog signal at the delay line input and producing progressively delayed signals at the output taps;
“n” differential analog multipliers, each having a multiplier signal input connected to the respective output tap of the delay
line, a tan weight input and a multiplier output, producing a multiplied signal which is a product of the respective progressively
delayed signal and the corresponding tap weight;
a summing tree having at least two layers of differential analog adders, each adder having at least two adder inputs and an
adder output;
the first layer of adders having collectively at least “n” adder inputs connected to the outputs of the “n” differential multipliers;
and each subsequent layer of adders having collectively a sufficient number of adder inputs to connect to the adder outputs
of the preceding layer; the last layer of differential adders having a single adder, the output of said single adder being
the FFE circuit output providing the equalized analog data signal, which is a sum of the “n” multiplied signals.
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