US 7,321,647 B2
Clock extracting circuit and clock extracting method
Kouji Matsuura, Chiba (Japan)
Assigned to Sony Corporation, (Japan)
Filed on Feb. 24, 2004, as Appl. No. 10/784,185.
Claims priority of application No. P2003-079706 (JP), filed on Mar. 24, 2003.
Prior Publication US 2004/0190667 A1, Sep. 30, 2004
Int. Cl. H04L 7/00 (2006.01)
U.S. Cl. 375—355  [375/360] 7 Claims
OG exemplary drawing
 
1. A clock extracting circuit for extracting a clock timing signal synchronous with input NRZ (Non-Return-to-Zero) type serial data from the serial data, said clock extracting circuit comprising:
oversampling means for oversampling said serial data using a reference clock signal of 2N times a frequency of said serial data, where N is an integer of two or more;
first timing detecting means for detecting the timing of 2N periods of said reference clock signal in a period of time in which the level of an output signal from said oversampling means remains unchanged;
second timing detecting means for detecting the timing of change in the level of the output signal from said oversampling means; and
clock timing signal outputting means for outputting the clock timing signal according to the timings detected by said first timing detecting means and said second timing detecting means.