CPC H10B 12/482 (2023.02) [H10B 12/50 (2023.02)] | 17 Claims |
1. A memory structure, comprising:
a substrate comprising a memory array region and a peripheral circuit region;
a plurality of bit line structures disposed in the memory array region of the substrate;
a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region;
a plurality of contacts disposed between the bit line structures and in the memory array region;
a dielectric layer disposed on the substrate and in the peripheral circuit region; and
a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure comprises the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures, wherein the protective structure further comprises a protective feature, wherein the protective feature is disposed between the dummy bit line structure and the dielectric layer.
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