CPC G11C 16/3427 (2013.01) [G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3459 (2013.01)] | 20 Claims |
18. A method of operating a memory device including a plurality of memory cell strings each including a plurality of memory cells coupled between a common source line and a bit line, a source select transistor coupled to a source select line between the common source line and the plurality of memory cells, a drain select transistor coupled to a drain select line between the bit line and the plurality of memory cells, and a plurality of dummy memory cells coupled between the plurality of memory cells and the source select transistor, the method comprising:
applying a first precharge voltage to the common source line in a first program loop among a plurality of program loops;
applying a first dummy voltage to at least one of a plurality of dummy word lines respectively coupled to the plurality of dummy memory cells in the first program loop;
applying a second precharge voltage higher than the first precharge voltage to the common source line in a second program loop after the first program loop among the plurality of program loops; and
applying a second dummy voltage higher than the first dummy voltage to the at least one dummy word line in the second program loop.
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