US 12,170,279 B2
Hybrid semiconductor device
Jung-Chien Cheng, Tainan (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Shi Ning Ju, Hsinchu (TW); Guan-Lin Chen, Hsinchu County (TW); Chih-Hao Wang, Hsinchu County (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/355,498.
Application 18/355,498 is a continuation of application No. 17/226,851, filed on Apr. 9, 2021, granted, now 11,710,737.
Claims priority of provisional application 63/146,036, filed on Feb. 5, 2021.
Prior Publication US 2023/0369321 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78645 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first number of nanostructures stacked one over another over a first anti-punch-through (APT) feature;
a second number of nanostructures stacked one over another over a second APT feature;
a dummy epitaxial feature disposed between and in contact with the first APT feature and the second APT feature; and
a source/drain feature disposed over the dummy epitaxial feature and in contact with sidewalls of the first number of nanostructures and sidewalls of the second number of nanostructures.