US 12,170,203 B2
Integrated circuit with conductive via formation on self-aligned gate metal cut
Jia-Chuan You, Hsinchu (TW); Chia-Hao Chang, Hsinchu (TW); Chu-Yuan Hsu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 21, 2022, as Appl. No. 17/581,787.
Claims priority of provisional application 63/225,104, filed on Jul. 23, 2021.
Prior Publication US 2023/0023916 A1, Jan. 26, 2023
Int. Cl. H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/28123 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823412 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a substrate;
a first transistor over the substrate and including:
a plurality of stacked first semiconductor nanostructures corresponding to channel regions of the first transistor; and
a first gate metal surrounding the first semiconductor nanostructures and having a top surface;
a second transistor over the substrate and including:
a plurality of stacked second semiconductor nanostructures corresponding to channel regions of the second transistor; and
a second gate metal surrounding the second semiconductor nanostructures and having a top surface;
a first dielectric isolation structure between the first gate metal and the second gate metal and having a top surface substantially coplanar with a top surface of the first gate metal;
a third gate metal on a first portion of the top surface of the first gate metal and on a first portion of the top surface of the second gate metal; and
a dielectric layer on the top surface of the dielectric isolation structure, on a second portion of the top surface of the first gate metal, and on a second portion of the top surface of the second gate metal, wherein the dielectric layer is in contact with the third gate metal above the first gate metal and above the second gate metal, wherein the first dielectric isolation structure is between each of the first semiconductor nanostructures and the second semiconductor nanostructures.