CPC H10B 51/20 (2023.02) [G11C 5/063 (2013.01); G11C 11/223 (2013.01); H01L 29/40111 (2019.08); H01L 29/40117 (2019.08); H01L 29/6656 (2013.01); H10B 51/10 (2023.02); H10B 53/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02)] | 20 Claims |
1. A method comprising:
forming a word line between a pair of dielectric layers, the word line formed of a first metal;
recessing a first sidewall of the word line from first sidewalls of the dielectric layers to form a first sidewall recess between the dielectric layers;
forming a first conductive spacer in the first sidewall recess and on the first sidewall of the word line, the first conductive spacer physically contacting the first sidewall of the word line, the first conductive spacer formed of a second metal, the second metal different from the first metal;
forming a memory film on a sidewall of the first conductive spacer and the first sidewalls of the dielectric layers;
forming a semiconductor film on a sidewall of the memory film; and
forming a bit line on a sidewall of the semiconductor film.
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