CPC H01L 25/18 (2013.01) [H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 2224/16145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01)] | 17 Claims |
1. A semiconductor device assembly comprising:
a substrate with a top side and a bottom side;
a first plurality of interconnects;
one or more memory devices electrically connected to the top side of the substrate via the first plurality of interconnects;
a second plurality of interconnects;
a processing unit connected to the top side of the substrate via the second plurality of interconnects, wherein the substrate is configured to enable the one or more memory devices and the processing unit to communicate directly with each other through the substrate;
a redistribution layer formed directly on the bottom side of the substrate and exclusive of any solder connections between the redistribution layer and the bottom side of the substrate, the redistribution layer comprising alternating conductive layers and dielectric layers;
a third plurality of interconnects electrically connected to the redistribution layer;
a plurality of back-end-of-line (BEOL) layers adjacent to the top side of the substrate; and
a complementary metal-oxide-semiconductor (CMOS) layer positioned between the plurality of BEOL layers and the redistribution layer.
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