CPC H04W 72/23 (2023.01) [H04L 1/1822 (2013.01); H04L 5/001 (2013.01); H04L 5/0023 (2013.01); H04L 5/0055 (2013.01); H04L 5/0094 (2013.01); H04W 4/06 (2013.01); H04W 72/21 (2023.01); H04W 72/0453 (2013.01)] | 16 Claims |
1. An integrated circuit to control a process, the process comprising:
receiving first downlink resource allocation information for a first downlink component carrier;
receiving second downlink resource allocation information for a second downlink component carrier, which is different from the first downlink component carrier;
receiving first downlink data on the first downlink component carrier in accordance with the first downlink resource allocation information;
receiving second downlink data on the second downlink component carrier in accordance with the second downlink resource allocation information;
receiving uplink resource allocation information for a uplink component carrier on one out of the first downlink component carrier and the second downlink component carrier;
transmitting uplink data on the uplink component carrier in accordance with the uplink resource allocation information; and
receiving an Acknowledgement/Negative-acknowledgement (ACK/NACK) signal for the uplink data in a physical hybrid-ARQ indicator channel (PHICH) only on said the downlink component carrier on which the uplink resource allocation information is received, a resource of the PHICH being determined based on the uplink resource allocation information.
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