US 12,170,282 B2
Semiconductor device with fin transistors and manufacturing method of such semiconductor device
Koichi Matsumoto, Kanagawa (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Filed by Sony Corporation, Tokyo (JP)
Filed on Oct. 12, 2023, as Appl. No. 18/485,440.
Application 16/443,319 is a division of application No. 15/588,072, filed on May 5, 2017, granted, now 10,373,955, issued on Aug. 6, 2019.
Application 18/485,440 is a continuation of application No. 17/399,222, filed on Aug. 11, 2021, granted, now 11,824,057.
Application 17/399,222 is a continuation of application No. 17/023,611, filed on Sep. 17, 2020, granted, now 11,121,133, issued on Sep. 14, 2021.
Application 17/023,611 is a continuation of application No. 16/443,319, filed on Jun. 17, 2019, granted, now 10,811,416, issued on Oct. 20, 2020.
Application 15/588,072 is a continuation of application No. 15/080,657, filed on Mar. 25, 2016, granted, now 9,741,814, issued on Aug. 22, 2017.
Application 15/080,657 is a continuation of application No. 14/709,047, filed on May 11, 2015, granted, now 9,331,077, issued on May 3, 2016.
Application 14/709,047 is a continuation of application No. 13/278,809, filed on Oct. 21, 2011, granted, now 9,059,312, issued on Jun. 16, 2015.
Claims priority of application No. 2010-243251 (JP), filed on Oct. 29, 2010.
Prior Publication US 2024/0047461 A1, Feb. 8, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28097 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 21/82385 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 27/0928 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/42356 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/4983 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a fin-type field effect transistor, the field effect transistor comprising:
a semiconductor base;
a semiconductor fin on the semiconductor base;
a gate electrode on the semiconductor base and the semiconductor fin;
in cross section, a gate insulating layer between the semiconductor base and the gate electrode, the gate insulating layer including a bottom layer between the semiconductor layer and the gate electrode and walls connected to and extending from the bottom layer, each of the gate insulating layer walls including an inside surface facing the gate electrode and an outside surface facing away from the gate electrode;
in the cross section, a first insulating film including walls, each first insulating layer wall having an inside surface and an outside surface, each inside surface of the first insulating film walls being adjacent a respective outside surface of one of the gate insulating layer walls; and
in the cross section, a second insulating film including walls, each second insulating film wall having an inside surface adjacent the outside surface of a respective one of the first insulating film walls,
wherein,
in the cross section, a distance along a gate length direction between the inside surface of one of the gate insulating layer walls and the inside surface of one of the second insulating film walls at first position along a gate height direction is greater than a distance between the inside surface of the one of the gate insulating layer walls and the inside surface of the one of the second insulating film walls at a second position along the gate height direction, the first position being between the semiconductor base and the second position,
in the cross section, the gate electrode is T-shaped with a rectangular top portion and a rectangular bottom portion; and
a top of the semiconductor fin is between first position and the second position and within the gate-height of the rectangular bottom portion of the gate electrode.