CPC H01L 29/24 (2013.01) [H10B 43/27 (2023.02)] | 20 Claims |
1. A semiconductor device comprising a memory cell array, the memory cell array comprising:
a first conductor over a base;
a first transistor over the first conductor, the first transistor comprising:
a second conductor comprising a first opening;
a first part of an insulator provided in contact with an inner side of the first opening; and
a first part of an oxide provided in contact with an inner side of the first part of the insulator; and
a second transistor stacked over the first transistor, the second transistor comprising:
a third conductor comprising a second opening;
a second part of the insulator provided in contact with an inner side of the second opening; and
a second part of the oxide provided in contact with an inner side of the second part of the insulator,
wherein the oxide comprises In, an element M, and Zn,
wherein the element M is at least one of Al, Ga, Y, and Sn, and
wherein the first part of the insulator is thicker than the second part of the insulator.
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