CPC H03L 7/085 (2013.01) [H03K 3/0315 (2013.01); H03K 5/14 (2013.01); H03L 7/0812 (2013.01); G04F 10/005 (2013.01); H03K 2005/00019 (2013.01)] | 15 Claims |
1. An electronic circuit comprising:
a first clock source terminal configured to receive a first clock signal;
a second clock source terminal configured to receive a second clock signal;
a set of latches having a first input and an output, wherein the first input of each latch is coupled to the first clock source terminal;
a multiplexer having a plurality of inputs and an output, each input of the plurality of inputs of the multiplexer is coupled to the output of a respective latch of the set of latches;
a time-to-digital converter having a first input, a second input, and a plurality of outputs, the first input coupled to the output of the multiplexer, and the second input coupled to the second clock source terminal; and
a phase determination circuit having a plurality of inputs coupled to the plurality of outputs of the time-to-digital converter, and configured to provide a phase difference between the first clock signal and the second clock signal.
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