US 12,169,463 B2
Method and devices for controlling operations of a central processing unit
Hakan Winbom, Sollentuna (SE)
Assigned to Nasdaq Technology AB, Stockholm (SE)
Filed by Nasdaq Technology AB, Stockholm (SE)
Filed on Jan. 10, 2023, as Appl. No. 18/095,037.
Application 18/095,037 is a continuation of application No. 17/485,808, filed on Sep. 27, 2021, granted, now 11,561,913.
Application 17/485,808 is a continuation of application No. 16/811,201, filed on Mar. 6, 2020, granted, now 11,138,138, issued on Oct. 5, 2021.
Application 16/811,201 is a continuation of application No. 15/866,760, filed on Jan. 10, 2018, granted, now 10,592,449, issued on Mar. 17, 2020.
Application 15/866,760 is a continuation of application No. 15/157,676, filed on May 18, 2016, granted, now 9,898,429, issued on Feb. 20, 2018.
Application 15/157,676 is a continuation of application No. 14/588,643, filed on Jan. 2, 2015, granted, now 9,355,047, issued on May 31, 2016.
Application 14/588,643 is a continuation of application No. 13/324,164, filed on Dec. 13, 2011, granted, now 8,930,737, issued on Jan. 6, 2015.
Prior Publication US 2023/0153256 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/00 (2006.01); G06F 1/08 (2006.01); G06F 1/3209 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 13/22 (2006.01); H04L 12/64 (2006.01)
CPC G06F 13/22 (2013.01) [G06F 1/08 (2013.01); G06F 1/3209 (2013.01); G06F 1/3234 (2013.01); G06F 1/324 (2013.01); H04L 12/6418 (2013.01); Y02B 70/10 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. Apparatus comprising:
processing circuitry that is associated with an input/output (I/O) range and that is configured to deliver input data to an application, wherein a first part of the processing circuitry is configured to operate at a first clock frequency; and
control circuitry configured to instruct the first part of the processing circuitry to poll the I/O range for input data to the application;
wherein the first part of the processing circuitry is configured to determine, in response to the processing circuitry having performed or about to perform a polling of the I/O range, whether the polling of the I/O range results in detection of input data at the I/O range for the application, and
wherein the first part of the processing circuitry is configured to operate, in response to a determination that a number of polls of the I/O range results in detection of input data at the I/O range for the application, at a second clock frequency that is greater than the first clock frequency.