US 12,169,703 B2
Graphics pipeline optimizations
Amit Ben-Moshe, Boxborough, MA (US); Brian Kenneth Bennett, Boxborough, MA (US); Qun Lin, Shanghai (CN); and David Ronald Oldcorn, Milton Keynes (GB)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 18, 2021, as Appl. No. 17/205,993.
Claims priority of provisional application 62/992,067, filed on Mar. 19, 2020.
Prior Publication US 2021/0294579 A1, Sep. 23, 2021
Int. Cl. G06F 8/34 (2018.01); G06F 3/0482 (2013.01); G06F 3/04845 (2022.01); G06F 8/41 (2018.01); G06T 1/20 (2006.01)
CPC G06F 8/34 (2013.01) [G06F 3/0482 (2013.01); G06F 3/04845 (2013.01); G06F 8/41 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A processor comprising:
one or more execution circuits configured to:
receive, via an interface, one or more shader programs and a pipeline state;
create an application programming interface (API) construct based on the one or more shader programs and the pipeline state;
generate resource utilization statistics, based on a compiled version of the API construct; and
circuitry configured to generate a graphical user interface (GUI) to display the resource utilization statistics and machine-level instructions corresponding to a graphics pipeline.