US 12,170,290 B2
Transistor substrate including wirings connecting between transistor and driver
Gen Koide, Tokyo (JP); Masaki Murase, Tokyo (JP); and Nobuyuki Ishige, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Jan. 12, 2024, as Appl. No. 18/411,390.
Application 18/411,390 is a continuation of application No. 18/163,460, filed on Feb. 2, 2023.
Application 18/163,460 is a continuation of application No. 17/523,508, filed on Nov. 10, 2021, granted, now 11,600,641, issued on Mar. 7, 2023.
Application 17/523,508 is a continuation of application No. 17/000,788, filed on Aug. 24, 2020, granted, now 11,205,665, issued on Dec. 21, 2021.
Application 17/000,788 is a continuation of application No. 16/783,659, filed on Feb. 6, 2020, granted, now 10,790,316, issued on Sep. 29, 2020.
Application 16/783,659 is a continuation of application No. 16/367,531, filed on Mar. 28, 2019, granted, now 10,600,822, issued on Mar. 24, 2020.
Application 16/367,531 is a continuation of application No. 16/040,141, filed on Jul. 19, 2018, granted, now 10,297,621, issued on May 21, 2019.
Application 16/040,141 is a continuation of application No. 15/901,918, filed on Feb. 22, 2018, granted, now 10,050,064, issued on Aug. 14, 2018.
Application 15/901,918 is a continuation of application No. 15/353,139, filed on Nov. 16, 2016, granted, now 9,935,134, issued on Apr. 3, 2018.
Application 15/353,139 is a continuation of application No. 15/081,224, filed on Mar. 25, 2016, granted, now 9,536,910, issued on Jan. 3, 2017.
Claims priority of application No. 2015-079124 (JP), filed on Apr. 8, 2015.
Prior Publication US 2024/0153964 A1, May 9, 2024
Int. Cl. H01L 27/12 (2006.01); H10K 59/131 (2023.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/124 (2013.01) [H01L 27/1244 (2013.01); H10K 59/131 (2023.02); H10K 59/1315 (2023.02); G02F 1/136286 (2013.01); G02F 1/13629 (2021.01); G02F 1/1368 (2013.01); H01L 29/78651 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A transistor substrate comprising:
a substrate;
a plurality of transistors;
a driver; and
a plurality of wirings electrically connected between the plurality of transistors and the driver,
wherein the plurality of wirings include a first wiring and a second wiring,
wherein each of the first wiring and the second wiring include a first region extending from the driver in a first direction, a second region extending in a predetermined direction at a first angle with respect to the first direction, and a third region extending at a second angle larger than the first angle with respect to the first direction,
wherein a line connecting a first bending point between the second region and the third region of the first wiring and a second bending point between the second region and the third region of the second wiring has an angle larger than the second angle with respect to the first direction, and
wherein each of the first wiring and the second wiring further include a fourth region extending at a third angle larger than the second angle with respect to the first direction, and a line connecting a third bending point between the third region and the fourth region of the first wiring and a fourth bending point between the third region and the fourth region of the second wiring has an angle smaller than the third angle with respect to the first direction.