CPC H03M 13/2909 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0661 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 11/10 (2013.01); G06F 11/1032 (2013.01); G06F 11/1048 (2013.01); G11C 11/4096 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); H03M 13/1575 (2013.01)] | 20 Claims |
16. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
an on-die error correction code (ECC) engine including a first latch and a second latch; and
a control logic circuit configured to control the on-die ECC engine,
wherein the on-die ECC engine, during a write operation, is configured to:
generate a scrambled main data by encoding a main data received from an external device with a random binary code received from the control logic circuit;
perform an ECC encoding on the scrambled main data to generate a parity data; and
store the scrambled main data and the parity data in a target page in the memory cell array, and
wherein the on-die ECC engine, during a read operation, is configured to:
read the scrambled main data and the parity data from the target page;
perform an ECC decoding on the scrambled main data based at least in part on the parity data to generate a syndrome in parallel with generating the main data by encoding the scrambled main data with the random binary code; and
correct at least one error bit, when present, in the main data based on the syndrome.
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