US 12,170,110 B2
Silicon-on-insulator (SOI) circuitry for low-voltage memory bit-line and word-line decoders
Lior Dagan, Ram-On (IL)
Assigned to Weebit Nano Ltd., Hod Hasharon (IL)
Filed by Weebit Nano Ltd., Hod Hasharon (IL)
Filed on Nov. 18, 2022, as Appl. No. 18/057,000.
Claims priority of provisional application 63/281,288, filed on Nov. 19, 2021.
Prior Publication US 2023/0162789 A1, May 25, 2023
Int. Cl. G11C 13/00 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01)
CPC G11C 13/0026 (2013.01) [G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 2213/53 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory comprises:
a memory array having a plurality of bit-line inputs and a plurality of word-line inputs;
a bit-line decoder having a plurality of bit-line outputs each bit-line output communicatively connected to a corresponding bit-line input of the memory array, wherein the bit-line decoder comprises a plurality of bit-line voltage supply circuits, wherein each bit-line voltage supply circuit comprises a first circuit comprising a first low-voltage field effect transistor (FET) of a first conductivity type connected in series with at least one second low-voltage FET of the first conductivity type and a second circuit comprising of a third low-voltage FET of a second conductivity type connected in series with at least one fourth low-voltage FET of the second conductivity type, wherein the first circuit is connected to the bit-line output and to a high-voltage supply input, and wherein the second circuit is connected to the bit-line output and to a high-voltage supply input; and
a control circuit having a plurality of control lines, the control circuit adapted to provide control signals to at least one of: the first low-voltage FET, the at least one second low-voltage FET, the third low-voltage FET, and the at least one fourth low-voltage FET, wherein the control circuit provides the control signals in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage at the high-voltage supply input.