US 12,170,334 B2
Isolation structures and methods of forming the same in field-effect transistors
Shi Ning Ju, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Guan-Lin Chen, Hsinchu County (TW); Chih-Hao Wang, Hsinchu County (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,664.
Application 18/446,664 is a continuation of application No. 17/464,517, filed on Sep. 1, 2021, granted, now 11,817,504.
Claims priority of provisional application 63/141,545, filed on Jan. 26, 2021.
Prior Publication US 2023/0387311 A1, Nov. 30, 2023
Int. Cl. H01L 29/78 (2006.01); B82Y 10/00 (2011.01); H01L 21/762 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7856 (2013.01) [H01L 21/76229 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/66439 (2013.01); H01L 29/6681 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); B82Y 10/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first stack of first semiconductor layers disposed on a substrate, wherein a topmost first semiconductor layer from the first stack of first semiconductor layers includes a first sidewall and an opposing second sidewall;
a first gate structure disposed on and interleaved with the first stack of first semiconductor layers, wherein the first gate structure includes a first gate electrode and a first gate dielectric layer;
a first isolation structure disposed adjacent to the first sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers, wherein the first gate dielectric layer and the first gate electrode fill space between the first isolation structure and the first sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers;
a second isolation structure disposed adjacent to and physically contacting the second sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers; and
a dielectric isolation structure disposed on the substrate, wherein the first isolation structure interfaces with a first portion of the dielectric isolation structure and the second isolation structure interfaces with a second portion of the dielectric isolation structure.