CPC H04W 76/27 (2018.02) [H04W 24/10 (2013.01); H04W 68/02 (2013.01); H04W 76/15 (2018.02); H04W 76/34 (2018.02)] | 20 Claims |
1. A processor, comprising:
memory storing instructions that, when executed, cause a master node to:
provide, to a user equipment (UE), a configuration associated with dual connectivity with a master cell group (MCG) associated with the master node and a secondary cell group (SCG) associated with a secondary node;
receive an indication of user inactivity regarding the UE from the secondary node;
provide, when the UE transitions from a radio resource control (RRC) connected mode to a RRC inactive mode, information to the secondary node that indicates release of part of the configuration;
receive, from the secondary node, a message indicating data activity for the UE; and
provide, when the UE transitions from the RRC inactive mode to the RRC connected mode, a configuration message to the secondary node for resumption of the configuration.
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