CPC H01L 23/49589 (2013.01) [H01L 21/02422 (2013.01); H01L 21/31055 (2013.01); H01L 21/76832 (2013.01); H01L 23/29 (2013.01); H01L 23/49827 (2013.01); H01L 23/5223 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02372 (2013.01); H01L 2924/19041 (2013.01)] | 20 Claims |
1. A method, comprising:
forming an interconnect structure on a substrate;
forming a through interposer via (TIV) structure on the interconnect structure;
attaching a die to the substrate and adjacent to the TIV structure;
forming a dielectric layer on a top surface of the TIV structure;
forming a metal layer on a top surface of the dielectric layer;
patterning the metal layer to form a side surface of the metal layer coplanar with a side surface of the TIV structure; and
forming a redistribution layer (RDL) on the die and the metal layer.
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