US 12,170,122 B2
Techniques for initializing memory error correction
Kai Wang, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 10, 2022, as Appl. No. 17/740,823.
Prior Publication US 2023/0368856 A1, Nov. 16, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/06 (2013.01); G11C 7/1048 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an activation command to open a set of rows, each row of the set of rows corresponding to a set of memory cells;
activating a plurality of word lines in response to the activation command, each word line of the plurality of word lines coupled with a respective row of the set of rows; and
storing a same logic state in a respective memory cell of each row of the set of rows based at least in part on activating the plurality of word lines.