CPC G02F 1/1368 (2013.01) [G02F 1/134363 (2013.01); G02F 1/136222 (2021.01); G02F 1/13624 (2013.01); G02F 1/136286 (2013.01)] | 9 Claims |
1. A pixel unit, comprising:
a first insulating layer;
a first pixel electrode located on a first side of the first insulating layer and including a plurality of first electrode strips;
a common electrode located on the first side of the first insulating layer and including a plurality of second electrode strips; wherein the second electrode strips and the first electrode strips are sequentially and alternately arranged in a first direction; and slits each are disposed between a second electrode strip in the second electrode strips and a first electrode strip in the first electrode strips that are adjacent to each other; and
a second pixel electrode located on a second side of the first insulating layer; wherein the second side of the first insulating layer is opposite to the first side of the first insulating layer; and the second pixel electrode is overlapped with at least a region where the slits are located;
wherein each of the plurality of first electrode strips includes at least two first electrode segments connected in sequence; and two adjacent first electrode segments have a first included angle therebetween, and the first included angle is greater than 0 degree and less than 180 degrees; and each of the plurality of second electrode strips includes at least two second electrode segments connected in sequence; and two adjacent second electrode segments have a second included angle therebetween, and the second included angle is greater than 0 degree and less than 180 degrees;
wherein a plane perpendicular to the first insulating layer and perpendicular to the first direction is a reference plane; wherein an included angle between each of at least one first electrode segment and the reference plane is 45±7 degrees, and an included angle between each of at least one second electrode segment and the reference plane is 45±7 degrees;
the pixel unit further comprises:
a first thin film transistor located on the second side of the first insulating layer; wherein a control electrode of the first thin film transistor is configured to be coupled to a scan signal line, a first electrode of the first thin film transistor is configured to be coupled to a first data voltage line, and a second electrode of the first thin film transistor is coupled to the plurality of first electrode strips of the first pixel electrode; and
a second thin film transistor located on the second side of the first insulating layer; wherein a control electrode of the second thin film transistor is configured to be coupled to the scan signal line, a first electrode of the second thin film transistor is configured to be coupled to a second data voltage line, and a second electrode of the second thin film transistor is coupled to the second pixel electrode; wherein
the common electrode is configured to be coupled to a common voltage line; and
the second pixel electrode includes a planar electrode and a third conductive connection portion, and the planar electrode is located on a side of a gate insulating layer of the second thin film transistor away from the first insulating layer; the gate insulating layer includes a fourth via; and the third conductive connection portion is connected to the second electrode of the second thin film transistor, and is connected to the planar electrode through the fourth via.
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