US 12,170,242 B2
Fan-out wafer level package structure
Jing-Cheng Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/064,624.
Application 15/206,638 is a division of application No. 13/656,053, filed on Oct. 19, 2012, granted, now 9,391,041, issued on Jul. 12, 2016.
Application 18/064,624 is a continuation of application No. 17/068,310, filed on Oct. 12, 2020, granted, now 11,527,464.
Application 17/068,310 is a continuation of application No. 16/166,592, filed on Oct. 22, 2018, granted, now 10,804,187, issued on Oct. 13, 2020.
Application 16/166,592 is a continuation of application No. 15/206,638, filed on Jul. 11, 2016, granted, now 10,109,567, issued on Oct. 23, 2018.
Prior Publication US 2023/0107519 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/5389 (2013.01); H01L 24/09 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/9222 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
planarizing a first surface, the first surface comprising a first external contact of a first die, a molding compound, a via located within a via die, and a second die, wherein the via extends from a first side of the via die to a second side of the via die, wherein the via has a straight sidewall as it extends from the first side to the second side; and
forming a redistribution layer over the first surface.