US 12,171,090 B2
Uniform layouts for SRAM and register file bit cells
Zheng Guo, Portland, OR (US); Clifford L. Ong, Portland, OR (US); Eric A. Karl, Portland, OR (US); and Mark T. Bohr, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 14, 2023, as Appl. No. 18/209,988.
Application 18/209,988 is a division of application No. 16/605,903, granted, now 11,737,253, previously published as PCT/US2017/038681, filed on Jun. 22, 2017.
Prior Publication US 2023/0328947 A1, Oct. 12, 2023
Int. Cl. H10B 10/00 (2023.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a substrate;
an eight transistor (8T) register file (RF) bit cell on the substrate, the 8T RF bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate;
first and second gate lines over the first, second, third and fourth active regions, the first and second gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction; and
third and fourth gate lines over the first and second active region, but not over the third and fourth active regions, the third and fourth gate lines parallel along the second direction of the substrate.