CPC H01L 27/1255 (2013.01) [G02F 1/136213 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/167 (2013.01); H01L 27/127 (2013.01); H01L 27/124 (2013.01)] | 17 Claims |
1. An array substrate comprising a plurality of pixel units distributed in a matrix and a plurality of scan lines and a plurality of data lines, the plurality of scan lines and the plurality of data lines being configured for driving the plurality of pixel units, each of the pixel units comprising:
a display region, comprising a pixel electrode and a common electrode, the pixel electrode at least partially overlapping with the common electrode in a direction perpendicular to the array substrate to form a first storage capacitor; and
a device region, being adjacent to the display region and comprising a drive transistor, the drive transistor being electrically connected to the pixel electrode, the drive transistor comprising a gate, an active layer, a source and a drain, the gate being electrically connected to a corresponding one of the plurality of scan lines, the source being electrically connected to a corresponding one of the plurality of data lines, the drain being electrically connected to the pixel electrode;
the gate extends in a direction towards the display region to form a first extension portion; the drain extends in the direction towards the display region to form a second extension portion, the second extension portion is electrically connected to the pixel electrode; the first extension portion and the second extension portion overlap in the direction perpendicular to the array substrate to form a second storage capacitor;
the pixel electrode partially extends to the device region to form a third extension portion, the third extension portion is electrically connected to the second extension portion through a conductive via; and
the third extension portion overlaps with the first extension portion in the direction perpendicular to the array substrate, to form a third storage capacitor.
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