CPC G11C 29/1201 (2013.01) [G11C 29/36 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/3602 (2013.01)] | 38 Claims |
1. A memory circuit, comprising:
a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
a word line drive circuit for each row having an output connected to drive the word line of the row;
a row decoder circuit configured to support two modes of memory circuit operation including: a first mode where the row decoder circuit actuates only one word line in the memory array during a memory read and a second mode where the row decoder circuit simultaneously actuates one word line per sub-array during the memory read; and
an input/output circuit for each column comprising:
a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
a column data output coupled to the plurality of bit line inputs; and
a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding bit line input;
wherein the input/output circuit for each column further comprises a logic gate having a first input coupled to the local bitline, a second input coupled to receive automated test pattern generated (ATPG) test pattern data, and an output coupled to the column data output and coupled to the sub-array data output.
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