CPC H01L 29/78618 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a stack of first and second semiconductor layers arranged in an alternating configuration on a substrate;
etching the substrate to form an opening adjacent to the stack of first and second semiconductor layers;
forming inner spacers on sidewalls of the first semiconductor layers;
forming a first epitaxial layer with first epitaxial portions on sidewalls of the second semiconductor layers, second epitaxial portions on sidewalls of the inner spacers, and a third epitaxial portion in the opening, wherein the first epitaxial portions are thicker than the second epitaxial portions;
performing an etching process on the first epitaxial layer;
forming a second epitaxial layer on the first epitaxial layer; and
forming a third epitaxial layer on the second epitaxial layer.
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