CPC G11C 16/3404 (2013.01) [G11C 16/16 (2013.01); G11C 8/00 (2013.01)] | 20 Claims |
1. A memory system comprising:
a non-volatile memory including a first block including a plurality of memory cells, the first block including a first sub-block and a second sub-block, the first sub-block including a first memory cell, the second sub-block including a second memory cell, the second memory cell being coupled in series to the first memory cell or coupled in parallel to the first memory cell with respect to a single bit line; and
a memory controller configured to instruct the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory, wherein
the memory controller is further configured to:
in response to a first value corresponding to the first sub-block having reached a first threshold value,
read first data from the first sub-block;
execute an error correction process on the first data read from the first sub-block; and
write the first data on which the error correction process has been executed into the non-volatile memory.
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