US 12,170,519 B2
Semiconductor device
Shoki Miyata, Kanagawa (JP); Yuto Yakubo, Kanagawa (JP); and Yoshiyuki Kurokawa, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jun. 23, 2022, as Appl. No. 17/847,241.
Claims priority of application No. 2021-112793 (JP), filed on Jul. 7, 2021; and application No. 2021-112798 (JP), filed on Jul. 7, 2021.
Prior Publication US 2023/0018223 A1, Jan. 19, 2023
Int. Cl. H03K 19/096 (2006.01); H03K 19/20 (2006.01); H03M 1/46 (2006.01)
CPC H03K 19/0963 (2013.01) [H03K 19/20 (2013.01); H03M 1/462 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a circuit comprising a first transistor, a second transistor, and a third transistor, and a fourth transistor,
wherein each of the first transistor and the third transistor is a p-channel transistor and comprises silicon in a channel formation region,
wherein each of the second transistor and the fourth transistor is an n-channel transistor and comprises a metal oxide in a channel formation region,
wherein the metal oxide comprises indium, an element M, and zinc,
wherein the element M is any one of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium,
wherein a gate of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring through the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the one of the source and the drain of the second transistor through the fourth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the one of the source and the drain of the second transistor, and
wherein each of the first transistor and the second transistor is capable of operating in a subthreshold region.