CPC G06F 9/30181 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3838 (2013.01); G06F 9/4843 (2013.01)] | 24 Claims |
1. A processor that executes an instruction set comprising one or more baseline instructions and one or more extended instructions, wherein the extended instructions are optional to implementation of the instruction set, the processor comprising:
a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each clock cycle of a clock circuit;
an instruction issue unit coupled to the time counter for receiving a first extended instruction, and issuing the first extended instruction with a preset execution time based on the time count, wherein the first extended instruction is referenced by an opcode reserved in the instruction set for an extended instruction; and
an execution queue coupled to the time counter and the instruction issue unit to receive the first extended instruction from the instruction issue unit and dispatch the first extended instruction to a functional unit based upon the time count.
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