US 12,170,315 B2
Field effect transistor with vertical nanowire in channel region and bottom spacer between the vertical nanowire and gate dielectric material
Ali Razavieh, Saratoga Springs, NY (US); and Haiting Wang, Clifton Park, NY (US)
Assigned to GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Malta, NY (US)
Filed on Jan. 6, 2022, as Appl. No. 17/569,897.
Prior Publication US 2023/0215917 A1, Jul. 6, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a bottom source/drain region;
a top source/drain region;
a gate structure extending between the bottom source/drain region and the top source/drain region; and
a vertical nanowire in a channel region of the gate structure,
wherein the gate structure comprises a gate dielectric material contacting the vertical nanowire and a gate metal material and further comprising a bottom spacer located between material of the vertical nanowire and the gate dielectric material.