US 12,170,231 B2
Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same
Chung-Wei Hsu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Kuan-Lun Cheng, Hsin-Chu (TW); Hou-Yu Chen, Hsinchu County (TW); Ching-Wei Tsai, Hsinchu (TW); Chih-Hao Wang, Hsinchu County (TW); Lung-Kun Chu, New Taipei (TW); Mao-Lin Huang, Hsinchu (TW); and Jia-Ni Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/815,079.
Application 17/815,079 is a division of application No. 16/926,470, filed on Jul. 10, 2020, granted, now 11,710,667.
Claims priority of provisional application 62/892,076, filed on Aug. 27, 2019.
Prior Publication US 2022/0367291 A1, Nov. 17, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823857 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02603 (2013.01); H01L 21/28185 (2013.01); H01L 21/31111 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42364 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/516 (2013.01); H01L 29/66742 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78696 (2013.01); H01L 2029/42388 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first device having a first type of conductivity, the first device including:
a first stack of first semiconductor layers, wherein each first semiconductor layer of the first stack is separated from each other;
a first interfacial layer wrapped around and physically contacting each first semiconductor layer of the first stack;
a first dipole gate dielectric layer wrapping around and physically contacting the first interfacial layer wrapped around each first semiconductor layer of the first stack; and
a first portion of a first capping layer wrapping around and physically contacting the first dipole gate dielectric layer; and
a second device having a second type of conductivity, the second type of conductivity being opposite the first type of conductivity, the second device including:
a second stack of second semiconductor layers, wherein each second semiconductor layer of the second stack is separated from each other;
a second interfacial layer wrapping around and physically contacting each second semiconductor layer of the second stack;
a first non-dipole gate dielectric layer wrapping around and physically contacting the second interfacial layer wrapped around each second semiconductor layer of the second stack; and
a second portion of the first capping layer wrapping around and physically contacting the first non-dipole gate dielectric layer, wherein the first portion of the first capping layer is non-contiguous with an upwardly-facing surface of the second portion of the first capping layer.