CPC G06F 11/1469 (2013.01) [G06F 9/52 (2013.01); G06F 11/0724 (2013.01); G06F 11/0796 (2013.01); G06F 11/1629 (2013.01); G06F 11/1658 (2013.01); G06F 11/181 (2013.01); G06F 11/183 (2013.01); G06F 11/2028 (2013.01); G06F 11/267 (2013.01); G06F 11/3013 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01)] | 20 Claims |
1. A parallel processing system comprising:
at least three processors configured for parallel operation, wherein the processors are included in a vehicle; and
state monitoring circuitry coupled to the processors, the state monitoring circuitry being configured to monitor a plurality of pipeline stages of individual processors included in a subset of the plurality of processors, wherein the state monitoring circuitry is configured to:
identify a first processor of the plurality of processors having at least one runtime state error associated with at least one pipeline stage, wherein identifying the first processor is based on comparing runtime states of the processors; and
state reload circuitry coupled to the processors, the state reload circuitry configured to update the runtime state of the at least one pipeline stage of the first processor based on one or more remaining processors of the subset, wherein the state reload circuitry is configured to adjust a voltage or common clock for the subset.
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