US 12,170,228 B2
Semiconductor device and methods of manufacturing
Hung-Yao Chen, Hsinchu (TW); Pin-Chu Liang, Hsinchu (TW); Hsueh-Chang Sung, Zhubei (TW); Pei-Ren Jeng, Chu-Bei (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,864.
Application 18/366,864 is a division of application No. 17/462,818, filed on Aug. 31, 2021, granted, now 11,948,840.
Prior Publication US 2023/0402326 A1, Dec. 14, 2023
Int. Cl. H01L 21/82 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first fin and a second fin disposed adjacent to a substrate, each of the first fin and the second fin being silicon;
a first isolation region interposed between the first fin and the second fin;
a third fin and a fourth fin disposed adjacent to the substrate, each of the third fin and the fourth fin being silicon-germanium;
a second isolation region interposed between the third fin and the fourth fin;
a first semiconductor layer disposed along the first fin and the second fin, the first semiconductor layer being a same composition as the first fin and the second fin, the first semiconductor layer physically contacting the first isolation region;
a first gate dielectric disposed over the first semiconductor layer;
a first gate disposed over the first gate dielectric;
a second semiconductor layer disposed adjacent to the third fin and the fourth fin, the second semiconductor layer comprising silicon-germanium, the second semiconductor layer physically contacting the second isolation region;
a second gate dielectric disposed over the second semiconductor layer; and
a second gate disposed over the second gate dielectric.