US 12,170,329 B2
High voltage MOSFET device with improved breakdown voltage
Anupam Dutta, Malta, NY (US); Vvss Satyasuresh Choppalli, Malta, NY (US); and Rajendran Krishnasamy, Malta, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,218.
Prior Publication US 2023/0290880 A1, Sep. 14, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/3215 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 21/3215 (2013.01); H01L 21/823493 (2013.01); H01L 29/0611 (2013.01); H01L 29/0623 (2013.01); H01L 29/66681 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first doped region disposed in the substrate;
a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other;
a third doped region disposed in the first doped region;
a fourth doped region disposed in the second doped region;
a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and
at least one high resistance region embedded in at least the second doped region, wherein the at least one high resistance region is vertically spaced apart from a top surface of the second doped region and vertically spaced apart from a bottom surface of the second doped region, wherein the at least one high resistance region comprises at least one amorphous semiconductor layer,
wherein the first doped region has a first conductivity type,
wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type,
wherein the first conductivity type and the second conductivity type are different.