CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G06F 12/0253 (2013.01); G06F 3/0688 (2013.01)] | 25 Claims |
1. A memory system, comprising:
one or more memory devices comprising a plurality of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive first data to be written to the one or more memory devices;
write, based at least in part on receiving the first data to be written to the one or more memory devices, the first data to a first set of cells of the plurality of memory cells using a first programming mode, the first programming mode being a single-level programming mode;
transfer, based at least in part on writing the first data to the first set of cells, the first data from the first set of cells to a second set of cells of the plurality of memory cells using a second programming mode, the second programming mode being a quad-level programming mode;
receive, after receiving the first data, second data to be written to the one or more memory devices; and
determine whether to write the second data to a third set of cells of the plurality of memory cells using the first programming mode or a third programming mode based at least in part on available cells of the plurality of memory cells that are ready for programming, wherein:
the plurality of memory cells are programmable using a fourth programming mode, and
the third programming mode and the fourth programming mode are tri-level programming modes, the third programming mode being associated with a first order for programming a lower page and one or more upper pages, and the fourth programming mode being associated with a second, different, order for programming the lower page and the one or more upper pages.
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