CPC G06F 1/10 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G11C 29/023 (2013.01); G11C 29/56004 (2013.01); H03K 21/38 (2013.01)] | 19 Claims |
1. A clock generating circuit comprising:
an oscillator configured to output an oscillator clock signal having a period based on a trim value;
a clock counter configured to count the oscillator clock signal for a reference time;
a finite state machine configured to obtain, from the clock counter, a count value of the oscillator clock signal that is counted, and in a test mode, compare the count value with a target count value and change the trim value based on a comparison result and determine a final trim value based on the trim value that is changed; and
a non-volatile memory that stores the final trim value that is determined,
wherein the oscillator is configured to output the oscillator clock signal having a shorter period as the trim value decreases.
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