US 12,170,262 B2
Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
David Auchere, Meylan (FR); Asma Hajji, Voiron (FR); Fabien Quercia, Saint Marcelin (FR); and Jerome Lopez, Saint Joseph de Riviere (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Dec. 15, 2022, as Appl. No. 18/081,884.
Application 18/081,884 is a division of application No. 16/835,793, filed on Mar. 31, 2020, granted, now 11,557,566.
Application 16/835,793 is a division of application No. 16/249,122, filed on Jan. 16, 2019, granted, now 10,643,970, issued on May 5, 2020.
Application 16/249,122 is a division of application No. 15/602,278, filed on May 23, 2017, granted, now 10,224,306, issued on Mar. 5, 2019.
Claims priority of application No. 1660622 (FR), filed on Nov. 3, 2016; application No. 1660623 (FR), filed on Nov. 3, 2016; and application No. 1660624 (FR), filed on Nov. 3, 2016.
Prior Publication US 2023/0121780 A1, Apr. 20, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01)
CPC H01L 24/85 (2013.01) [H01L 23/3157 (2013.01); H01L 23/552 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/45565 (2013.01); H01L 2224/48992 (2013.01); H01L 2224/48997 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/8592 (2013.01); H01L 2924/00014 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method, comprising the following steps:
placing a first electrical connection wire between a first electrical connection pad of an electronic chip and a second electrical connection pad of a carrier substrate to which the electronic chip is mounted and forming first electrical junctions between ends of the first electrical connection wire and the first and second electrical connection pads;
placing a second electrical connection wire between a third electrical connection pad of the electronic chip and a fourth electrical connection pad of the carrier substrate to which the electronic chip is mounted and forming second electrical junctions between ends of the second electrical connection wire and the third and fourth electrical connection pads;
producing a dielectric coating made of a dielectric material, which completely covers the first electrical connection wire, but does not cover the second electrical connection wire, and completely covers the first electrical junctions, but does not cover the second electrical junctions, and further covers each of the first and second electrical connection pads without completely covering the third and fourth electrical connection pads; and
producing a conductive shield made of an electrically conductive material which at least partially covers said dielectric coating at said first and second electrical connection pads and completely covers said dielectric coating at said first electrical junctions and further completely surrounds said dielectric coating at said first electrical connection wire; and
wherein the electrically conductive material of said conductive shield is in direct contact with the second electrical connection wire.