US 12,170,117 B2
3D NAND memory with built-in capacitor
Yu-Chung Lien, San Jose, CA (US); Ching-Huang Lu, Fremont, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 2, 2022, as Appl. No. 17/879,356.
Prior Publication US 2024/0046998 A1, Feb. 8, 2024
Int. Cl. G11C 16/30 (2006.01)
CPC G11C 16/30 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a set of memory components of a memory sub-system, the set of memory components comprising:
a first memory block comprising first units of linearly arranged memory cells;
a second memory block comprising second units of linearly arranged memory cells; and
a slit portion dividing the first and second memory blocks, the slit portion comprising a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells, holdup power being provided to the set of memory components from the capacitor in response to a power failure event associated with a regulator supply.