US 12,170,259 B2
Semiconductor package and method of fabricating the same
Ju Bin Seo, Seongnam-si (KR); Seok Ho Kim, Hwaseong-si (KR); and Kwang Jin Moon, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 7, 2022, as Appl. No. 17/715,103.
Claims priority of application No. 10-2021-0116317 (KR), filed on Sep. 1, 2021.
Prior Publication US 2023/0060360 A1, Mar. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 22/32 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/039 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08057 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/08237 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor chip including:
a first semiconductor substrate, the first semiconductor substrate having first and second surfaces that are opposite to each other,
a first semiconductor element layer and a first wiring structure, which are sequentially stacked on the first surface of the first semiconductor substrate,
first connecting pads and first test pads on the first wiring structure, the first connecting pads and the first test pads being connected to the first wiring structure, and
first front-side bonding pads connected to the first connecting pads; and
a second semiconductor chip bonded to the first semiconductor chip, the second semiconductor chip including:
a second semiconductor substrate, the second semiconductor substrate having a third surface and a fourth surface that are opposite to each other, and the fourth surface facing the first surface of the first semiconductor substrate,
a second semiconductor element layer and a second wiring structure, which are sequentially stacked on the third surface of the second semiconductor substrate, and
first back-side bonding pads on the fourth surface of the second semiconductor substrate, the first back-side bonding pads being bonded to the first front-side bonding pads of the first semiconductor chip,
wherein the first test pads of the first semiconductor chip are not electrically connected to the second semiconductor chip.