US 12,170,325 B2
Method of manufacturing a semiconductor device and a semiconductor device
Cheng-Wei Chang, Taipei (TW); Shahaji B. More, Hsinchu (TW); Yi-Ying Liu, Hsinchu (TW); and Yueh-Ching Pai, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/231,419.
Application 18/231,419 is a division of application No. 17/577,952, filed on Jan. 18, 2022, granted, now 11,973,124.
Claims priority of provisional application 63/275,696, filed on Nov. 4, 2021.
Prior Publication US 2023/0378316 A1, Nov. 23, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01)
CPC H01L 29/66507 (2013.01) [H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H01L 29/66598 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of semiconductor bodies disposed and vertically arranged over a substrate, each of the plurality of semiconductor bodies including a channel region;
a gate dielectric layer disposed on and wrapping around the channel region of each of the plurality of semiconductor bodies;
a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region;
a source/drain region including a source/drain epitaxial layer; and
a source/drain contact disposed over and in electrical contact with the source/drain epitaxial layer, wherein:
a first silicide layer is disposed on the source/drain epitaxial layer, and
a second silicide layer different from the first silicide layer is disposed on the first silicide layer.