US 12,169,629 B2
Varying memory erase depth according to block characteristics
Sriteja Yamparala, Boise, ID (US); and Tawalin Opastrakoon, Boise, ID (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 19, 2023, as Appl. No. 18/223,933.
Claims priority of provisional application 63/402,422, filed on Aug. 30, 2022.
Prior Publication US 2024/0069730 A1, Feb. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/064 (2013.01); G06F 3/0652 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
identifying one or more candidate memory blocks that are available for garbage collection;
determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block;
erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block;
receiving a request to write data subsequent to erasing the candidate memory blocks; and
responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks.