CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] | 20 Claims |
1. A control circuit comprising:
a latch circuit configured to generate a first light sleep signal according to a sense amplifier enable signal and to provide the first light sleep signal to a bit line reading switch so the bit line reading switch is cutoff after a sense amplifier is enabled, wherein the latch circuit comprises a logic gate configured to compare the sense amplifier enable signal and a clock signal.
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