US 12,170,336 B2
Oxide semiconductor transistor, method of manufacturing the same, and memory device including oxide semiconductor transistor
Kwanghee Lee, Hwaseong-si (KR); and Sangwook Kim, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 2, 2021, as Appl. No. 17/540,607.
Claims priority of application No. 10-2021-0067899 (KR), filed on May 26, 2021.
Prior Publication US 2022/0384656 A1, Dec. 1, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 21/02565 (2013.01); H01L 29/66969 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An oxide semiconductor transistor comprising:
a substrate;
first and second compound layers on the substrate;
a channel layer contacting the first and second compound layers;
a first electrode facing a portion of the channel layer;
a second electrode facing the first compound layer with the channel layer between the first compound layer and the second electrode; and
a third electrode facing the second compound layer with the channel layer between the second compound layer and the third electrode,
wherein, in the channel layer, an oxygen concentration of a region facing the first electrode is greater than that of remaining regions of the channel layer, and
the first and second compound layers include a metal having higher oxygen reactivity compared to an oxygen reactivity of the second and third electrodes.