US 12,170,129 B2
Data receiving circuit, data receiving system and storage device
Feng Lin, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 27, 2022, as Appl. No. 17/953,413.
Application 17/953,413 is a continuation of application No. PCT/CN2022/105291, filed on Jul. 12, 2022.
Claims priority of application No. 202210726556.3 (CN), filed on Jun. 23, 2022.
Prior Publication US 2023/0023730 A1, Jan. 26, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1048 (2013.01); G11C 7/109 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data receiving circuit, comprising:
a first amplification module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal respectively through a first node and a second node;
a decision feedback control module, configured to generate a second sampling clock signal in response to an enable signal;
a decision feedback equalization module, connected to the first node and the second node, wherein the decision feedback equalization module is configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and based on a feedback signal to adjust the first voltage signal and the second voltage signal, and stop performing the decision feedback equalization when the enable signal is in a second level value interval, the feedback signal being obtained based on previously received data; and
a second amplification module, configured to amplify a voltage difference between the first voltage signal and the second voltage signal, and output a first output signal and a second output signal respectively through a third node and a fourth node.