CPC G09G 5/005 (2013.01) [G09G 5/18 (2013.01)] | 20 Claims |
1. A method of display processing, comprising:
receiving a hardware Vsync signal from a display using a video mode;
generating a hardware timestamp signal based on the hardware Vsync signal;
determining a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames;
determining whether the delay for the pulse is over a threshold; and
controlling rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold.
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