US 12,171,093 B2
NAND string utilizing floating body memory cell
Benjamin S. Louie, Fremont, CA (US); Jin-Woo Han, San Jose, CA (US); and Yuniarto Widjaja, San Jose, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Oct. 7, 2023, as Appl. No. 18/377,794.
Application 15/161,493 is a division of application No. 14/267,112, filed on May 1, 2014, granted, now 9,368,625, issued on Jun. 14, 2016.
Application 18/377,794 is a continuation of application No. 17/868,722, filed on Jul. 19, 2022, granted, now 11,818,878.
Application 17/868,722 is a continuation of application No. 17/219,564, filed on Mar. 31, 2021, granted, now 11,417,658, issued on Aug. 16, 2022.
Application 17/219,564 is a continuation of application No. 16/706,148, filed on Dec. 6, 2019, granted, now 10,991,697, issued on Apr. 27, 2021.
Application 16/706,148 is a continuation of application No. 16/132,675, filed on Sep. 17, 2018, granted, now 10,546,860, issued on Jan. 28, 2020.
Application 16/132,675 is a continuation of application No. 15/628,931, filed on Jun. 21, 2017, granted, now 10,103,148, issued on Oct. 16, 2018.
Application 15/628,931 is a continuation of application No. 15/161,493, filed on May 23, 2016, granted, now 9,704,578, issued on Jul. 11, 2017.
Claims priority of provisional application 61/818,305, filed on May 1, 2013.
Claims priority of provisional application 61/829,262, filed on May 31, 2013.
Prior Publication US 2024/0040767 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 12/00 (2023.01); G11C 5/06 (2006.01); G11C 11/4096 (2006.01); G11C 11/4099 (2006.01); G11C 16/04 (2006.01); H01L 21/265 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01); H10B 69/00 (2023.01)
CPC H10B 12/20 (2023.02) [G11C 5/063 (2013.01); G11C 11/4096 (2013.01); G11C 11/4099 (2013.01); G11C 16/0416 (2013.01); G11C 16/0483 (2013.01); H01L 21/26586 (2013.01); H01L 23/528 (2013.01); H01L 27/0886 (2013.01); H01L 29/1087 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/7841 (2013.01); H01L 29/785 (2013.01); H10B 12/50 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02); H10B 69/00 (2023.02); G11C 2211/4016 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells are serially connected to one another, and wherein each said semiconductor memory cell includes:
a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, said floating body region have a first conductivity type selected from p-type conductivity type and n-type conductivity type;
said floating body region having a bottom surface bounded by an insulator layer;
a first region in electrical contact with said floating body region, said first region exposed at or proximal to a top surface of said floating body region and extending to contact said insulator layer;
a second region in electrical contact with said floating body region and spaced apart from said first region, said second region exposed at or proximal to said top surface of said floating body region and extending into said floating body region, wherein said floating body region underlies said second region such that said second region does not extend to contact said insulator layer;
a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region exposed at or proximal to said top surface of said floating body region and extending to contact said insulator layer; and
a gate positioned between said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell; and
wherein said semiconductor memory cell has only one said gate.