US 12,170,109 B2
Hybrid resistive memory
Elisa Vianello, Grenoble (FR); and Jean-François Nodin, Grenoble (FR)
Assigned to COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by Commissariat à I'Energie Atomique et aux Energies Alternatives, Paris (FR)
Filed on Nov. 10, 2021, as Appl. No. 17/454,311.
Claims priority of application No. 20306367 (EP), filed on Nov. 12, 2020.
Prior Publication US 2022/0148653 A1, May 12, 2022
Int. Cl. G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/0004 (2013.01) [G11C 13/0011 (2013.01); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02); G11C 2213/79 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a transistor layer;
a plurality of first memory elements positioned in a first level above the transistor layer;
a plurality of filament switching resistive memory elements positioned in a second level higher than the first level, wherein the first memory elements and the filament switching resistive memory elements are positioned in different levels of a same region of the device;
at least one first interconnection level separating the first and second levels, wherein the at least one first interconnection level is dedicated to the routing of the first memory elements; and
at least one second interconnection level, separating the first and second levels or being higher than the second level, dedicated to the routing of the filament switching resistive memory elements.