CPC H10B 43/27 (2023.02) [H01L 29/40117 (2019.08); H01L 29/4234 (2013.01)] | 19 Claims |
1. A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and dielectric layers; and
a channel structure extending through the stack structure along a first direction, the channel structure comprising a semiconductor channel, and a memory film over the semiconductor channel, and the memory film comprising a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer,
wherein the storage layer is separated by the dielectric layers into a plurality of storage sections each in contact with corresponding adjacent dielectric layers, and
wherein the blocking layer, the storage layer, and the tunneling layer are fully separated by the dielectric layers into a plurality of sections isolated from each other.
|