US 12,169,222 B2
Delay measurement system and measurement method
Shang Hsien Yang, Hsinchu (TW); Chung-Chieh Yang, Hsinchu County (TW); Yung-Chow Peng, Hsinchu (TW); and Chih-Chiang Chang, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Feb. 15, 2022, as Appl. No. 17/671,999.
Prior Publication US 2023/0258721 A1, Aug. 17, 2023
Int. Cl. G01R 31/319 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01); H03K 3/037 (2006.01); H03K 5/26 (2006.01)
CPC G01R 31/31922 (2013.01) [G01R 31/31725 (2013.01); G01R 31/318328 (2013.01); G01R 31/3191 (2013.01); H03K 3/037 (2013.01); H03K 5/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delay measurement system, comprising:
a delay control device, configured to generate a second signal in response to a first signal, wherein a rising edge of the second signal delays a first delay time with respect to a rising edge of the first signal, and the first delay time is controlled in response to an output signal of a plurality of D flip-flops;
a first delay controlled delay line (DCDL) device, configured to generate a fourth signal in response to the first signal, wherein the fourth signal delays a first offset time with respect to the first signal, a third signal is generated by a device under test (DUT) external to the first DCDL device in response to the fourth signal, and the first offset time is configured to align the rising edges of the second signal and the third signal; and
the plurality of D flip-flops, configured to compare the first delay time with a second delay time and output the output signal, wherein a rising edge of the third signal delays the second delay time with respect to the rising edge of the first signal.