US 12,170,244 B2
High-throughput additively manufactured power delivery vias and traces
Adel Elsherbini, Tempe, AZ (US); Feras Eid, Chandler, AZ (US); Georgios Dogiamis, Chandler, AZ (US); Henning Braunisch, Phoenix, AZ (US); Beomseok Choi, Chandler, AZ (US); William J. Lambert, Tempe, AZ (US); Stephen Morein, Chandler, AZ (US); Ahmed Abou-Alfotouh, Chandler, AZ (US); and Johanna Swan, Scottsdale, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/914,062.
Prior Publication US 2021/0407903 A1, Dec. 30, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H05K 1/11 (2006.01); H05K 3/14 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76879 (2013.01); H01L 23/53228 (2013.01); H05K 1/115 (2013.01); H05K 3/14 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) die package substrate comprising:
a first trace upon, or embedded within, a dielectric material, wherein the first trace comprises a first metal;
a first via coupled to the first trace, wherein the first via comprises the first metal;
a second trace upon, or embedded within, the dielectric material; and
a second via coupled to the second trace, wherein at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal, wherein the second metal has a greater void % area than the first metal and wherein the second metal has a void % area of at least 0.1%.