US 12,170,323 B2
Nano transistors with source/drain having side contacts to 2-D material
Chao-Ching Cheng, Hsinchu (TW); Yi-Tse Hung, Hsinchu (TW); Hung-Li Chiang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); Lain-Jong Li, Hsinchu (TW); and Jin Cai, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 6, 2023, as Appl. No. 18/365,995.
Application 18/365,995 is a division of application No. 17/351,622, filed on Jun. 18, 2021, granted, now 11,955,527.
Claims priority of provisional application 63/107,041, filed on Oct. 29, 2020.
Prior Publication US 2023/0387235 A1, Nov. 30, 2023
Int. Cl. H01L 29/00 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/2003 (2013.01); H01L 29/66446 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an n-type transistor comprising:
a first channel comprising a transition metal dichalcogenide;
a first dielectric layer over and contacting the first channel;
a second dielectric layer under and contacting the first channel;
a first metal source/drain region contacting first sidewalls of the first channel, the first dielectric layer, and the second dielectric layer; and
a first gate stack comprising a first portion over and contacting the first dielectric layer, and a second portion under and contacting the second dielectric layer.