CPC H10K 50/844 (2023.02) [H10K 59/131 (2023.02)] | 14 Claims |
1. A display apparatus, comprising:
a substrate including a display area on which a plurality of pixels are disposed, a camera hole in the display area, and a first non-display area between the display area and the camera hole,
wherein the first non-display area includes a disconnection area where at least one dam structure is disposed,
wherein each of the plurality of pixels includes a first transistor and a second transistor on a gate electrode of the first transistor, and a plurality of buffer layers below the first transistor and the second transistor,
wherein the plurality of buffer layers extend to the first non-display area, and
wherein the first non-display area includes a high potential power line and a gate line between the at least one dam structure and the display area.
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