US 12,170,121 B2
Semiconductor memory device including command log register and command log output method thereof
Youngsan Kang, Suwon-si (KR); Donghee Kim, Suwon-si (KR); Jungho Jung, Suwon-si (KR); and Jun-Ho Jo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 20, 2022, as Appl. No. 17/949,000.
Claims priority of application No. 10-2022-0046929 (KR), filed on Apr. 15, 2022.
Prior Publication US 2023/0335209 A1, Oct. 19, 2023
Int. Cl. G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/36 (2013.01) [G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory core comprising memory cells and configured to output core data stored in the memory cells in response to a read request;
a command decoder configured to decode at least one command input from an external device;
a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal; and
a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.