CPC H01L 29/66507 (2013.01) [H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H01L 29/66598 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a plurality of semiconductor bodies disposed and vertically arranged over a substrate, each of the plurality of semiconductor bodies including a channel region;
a gate dielectric layer disposed on and wrapping around the channel region of each of the plurality of semiconductor bodies;
a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region;
a source/drain region including a source/drain epitaxial layer; and
a source/drain contact disposed over and in electrical contact with the source/drain epitaxial layer, wherein:
a first silicide layer is disposed on the source/drain epitaxial layer, and
a second silicide layer different from the first silicide layer is disposed on the first silicide layer.
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