US 12,170,256 B2
Contact pad fabrication process for a semiconductor product
Sudtida Lavangkul, Murphy, TX (US); and Yung Shan Chang, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 27, 2021, as Appl. No. 17/459,849.
Prior Publication US 2023/0061951 A1, Mar. 2, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/311 (2006.01); H01L 21/44 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/31144 (2013.01); H01L 23/53295 (2013.01); H01L 24/03 (2013.01); H01L 2224/03466 (2013.01); H01L 2224/03845 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05583 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05664 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05684 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a dielectric layer over a top level metallization layer of a semiconductor process wafer;
patterning the dielectric layer using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer, wherein the contact pad opening is aligned to a contact pad defined in the top level metallization layer;
depositing a metal layer over the patterned dielectric layer including within the contact pad opening; and
removing a portion of the metal layer by a chemical mechanical polishing (CMP) process, a remaining portion of the metal layer having a sloped sidewall.
 
25. An integrated circuit, comprising:
a semiconductor substrate including a top level metallization layer; and
a plurality of contact pad structures formed in a dielectric layer deposited over the top level metallization layer, the plurality of contact pad structures each having a sloped sidewall profile,
wherein the plurality of contact pad structures are formed by patterning the dielectric layer in a grayscale mask process using a photoresist exposed with a photomask having a dithered region surrounding a mask area that defines a contact pad opening in the dielectric layer corresponding to a respective one of a plurality of contact pads defined in the top level metallization layer, the dithered region varying in density from the surrounded mask area to a mask field area surrounding the dithered region.