US 12,170,257 B2
Three-dimensional memory devices and methods for forming the same
Liang Chen, Wuhan (CN); Wei Liu, Wuhan (CN); Yanhong Wang, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Kun Zhang, Wuhan (CN); and Yuancheng Yang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 21, 2021, as Appl. No. 17/480,852.
Application 17/480,852 is a continuation of application No. PCT/CN2021/103697, filed on Jun. 30, 2021.
Prior Publication US 2023/0005856 A1, Jan. 5, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
an array of NAND memory strings; and
a first semiconductor layer in contact with sources of the array of NAND memory strings; and
a second semiconductor structure comprising:
a second semiconductor layer;
a first peripheral circuit of the array of NAND memory strings, the first peripheral circuit comprising first transistors in contact with a first side of the second semiconductor layer facing the first semiconductor structure;
a first interconnect layer, comprising first interconnects coupled to the first transistors;
a second peripheral circuit of the array of NAND memory strings, the second peripheral circuit comprising second transistors in contact with a second side of the second semiconductor layer opposite to the first side; and
a second interconnect layer comprising second interconnects coupled to the second transistors;
wherein a first operating voltage of the first peripheral circuit closer to the NAND memory strings with respect to the second peripheral circuit is higher than a second operating voltage of the second peripheral circuit farther from the NAND memory strings with respect to the first peripheral circuit, and a first thermal budget of a first material of the first interconnects is higher than a second thermal budget of a second material of the second interconnects.