US 12,170,324 B2
Transistors and arrays of elevationally-extending strings of memory cells
Ramanathan Gandhi, Boise, ID (US); Augusto Benvenuti, Lallio (IT); and Giovanni Maria Paolucci, Milan (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Nov. 15, 2022, as Appl. No. 17/987,779.
Application 17/987,779 is a continuation of application No. 17/182,808, filed on Feb. 23, 2021, granted, now 11,538,919.
Prior Publication US 2023/0075673 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/51 (2006.01)
CPC H01L 29/517 (2013.01) [H01L 29/513 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A transistor comprising:
a channel region having a frontside and a backside;
a gate adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region;
a charge-blocking region adjacent the gate;
a charge-storage material adjacent the charge-blocking region, the gate insulator being between the channel region and the charge-storage material;
an insulating material having net negative charge and having a first side and a second side, wherein the second side is opposing the first side and adjacent the backside of the channel region; and
a dielectric material adjacent the first side of the insulating material.