US 12,170,247 B2
Semiconductor memory device
Tadayoshi Watanabe, Yokkaichi Mie (JP); and Kouji Matsuo, Ama Aichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 14, 2022, as Appl. No. 17/944,830.
Claims priority of application No. 2022-046554 (JP), filed on Mar. 23, 2022.
Prior Publication US 2023/0307359 A1, Sep. 28, 2023
Int. Cl. H01L 23/528 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/528 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
13. A semiconductor memory device comprising:
a substrate; and
a plurality of first memory layers and a plurality of second memory layers arranged in alternation in a first direction intersecting with a surface of the substrate, wherein
the substrate includes:
a plurality of local block regions arranged in a second direction intersecting with the first direction; and
a hook-up region arranged in the second direction with respect to the plurality of local block regions,
in the plurality of local block regions, each of the plurality of first memory layers and the plurality of second memory layers includes:
a plurality of memory strings extending in the second direction and arranged in a third direction intersecting with the first direction and the second direction; and
a first wiring extending in the third direction and connected to the plurality of memory strings in common,
in the hook-up region, each of the plurality of first memory layers and the plurality of second memory layers includes:
a signal amplifier circuit electrically connected to the first wiring; and
a second wiring connected to the signal amplifier circuit, wherein
in the plurality of local block regions, each of the plurality of first memory layers includes a first switch transistor connected to the second wiring,
in the plurality of local block regions, each of the plurality of second memory layers includes a second switch transistor connected to the second wiring, and
the hook-up region includes:
a first via-contact electrode extending in the first direction and connected to the second wiring included in one of the plurality of first memory layers via the first switch transistor; and
a second via-contact electrode extending in the first direction and connected to the second wiring included in one of the plurality of second memory layers via the second switch transistor.