CPC G11C 29/36 (2013.01) [G11C 29/1201 (2013.01); G11C 29/12015 (2013.01)] | 20 Claims |
1. A semiconductor memory device comprising:
a memory core comprising memory cells and configured to output core data stored in the memory cells in response to a read request;
a command decoder configured to decode at least one command input from an external device;
a command log register configured to sequentially store the at least one command in response to a register enable signal and output the at least one command as a command log in response to a command log read signal; and
a mode register set configured to generate the register enable signal or the command log read signal in response to a mode register set command transmitted to the command decoder.
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