CPC G11C 29/702 (2013.01) [G06F 11/1666 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] | 20 Claims |
1. A method, comprising:
providing a first column of memory cells, wherein a first local redundancy decoder circuit is operably connected to the first column of memory cells;
providing a second column of memory cells immediately adjacent the first column of memory cells, wherein a second local redundancy decoder circuit is operably connected to the second column of memory cells and to the first column of memory cells, and wherein the first local redundancy decoder circuit differs from the second local redundancy decoder circuit and includes two inverters operable connected in series;
providing a first pre-decoder circuit operably connected to the first local redundancy decoder circuit.
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