CPC G11C 7/22 (2013.01) [G11C 7/1063 (2013.01); G11C 7/1066 (2013.01)] | 20 Claims |
1. A synchronization circuit for an interconnection protocol, the synchronization circuit comprising:
a first synchronization circuit module configured to convert first control information of a first clock domain, wherein the first control information is output by a data link layer receiver of a first device, into second control information of a second clock domain; and
a second synchronization circuit module, coupled to the first synchronization circuit module, configured to convert the second control information of the second clock domain, wherein the second control information is output by the first synchronization circuit module, into third control information of a third clock domain to output the third control information of the third clock domain to a data link layer transmitter of the first device;
wherein the first control information output by the data link layer receiver is at least one signal of the first clock domain;
wherein the third control information output by the second synchronization circuit module is at least one signal of the third clock domain; and
wherein the first clock domain, the second clock domain, and the third clock domain are asynchronous.
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