US 12,170,125 B2
Memory device and electronic device
Chien-Yu Huang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); and Hua-Tai Shieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,752.
Application 18/362,752 is a continuation of application No. 17/843,591, filed on Jun. 17, 2022, granted, now 11,756,647.
Application 17/843,591 is a continuation of application No. 17/135,043, filed on Dec. 28, 2020, granted, now 11,367,507, issued on Jun. 21, 2022.
Application 17/135,043 is a continuation of application No. 16/509,178, filed on Jul. 11, 2019, granted, now 10,878,934, issued on Dec. 29, 2020.
Claims priority of provisional application 62/698,640, filed on Jul. 16, 2018.
Prior Publication US 2023/0410935 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 11/16 (2006.01); G11C 7/12 (2006.01); G11C 8/10 (2006.01)
CPC G11C 29/702 (2013.01) [G06F 11/1666 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a first column of memory cells, wherein a first local redundancy decoder circuit is operably connected to the first column of memory cells;
providing a second column of memory cells immediately adjacent the first column of memory cells, wherein a second local redundancy decoder circuit is operably connected to the second column of memory cells and to the first column of memory cells, and wherein the first local redundancy decoder circuit differs from the second local redundancy decoder circuit and includes two inverters operable connected in series;
providing a first pre-decoder circuit operably connected to the first local redundancy decoder circuit.