CPC H01L 29/7827 (2013.01) [H01L 29/0657 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66924 (2013.01); H01L 29/7788 (2013.01); H01L 29/7789 (2013.01); H01L 29/8083 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
at least one vertical transistor, comprising:
a substrate comprising a first semiconductor material;
an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the first semiconductor material;
a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, wherein the sidewall heterojunction layer comprises a second semiconductor material, wherein the first and second semiconductor materials have different bandgaps; and
an isolation region positioned between the 3D structures.
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