CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] | 14 Claims |
1. A semiconductor memory device, comprising:
a substrate with a complementary metal oxide semiconductor (CMOS) circuit;
a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked over the substrate in a vertical direction;
a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and
a plurality of conductive layers disposed over the gate stacked body; and
a bit line that is coupled to a second end of the channel structure, the bit line disposed between the substrate and the gate stacked body,
wherein each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.
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