US 12,171,100 B2
Semiconductor memory device and method of manufacturing semiconductor memory device
Byung Wook Bae, Icheon-si (KR); and Eun Seok Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 11, 2022, as Appl. No. 17/717,896.
Claims priority of application No. 10-2021-0141663 (KR), filed on Oct. 22, 2021.
Prior Publication US 2023/0125409 A1, Apr. 27, 2023
Int. Cl. H10B 43/40 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/40 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a gate stack including a cell array region and a gate contact region, and comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked;
a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers alternately stacked in a direction in which the plurality of first interlayer insulating patterns and the plurality of conductive patterns are alternately stacked;
a plurality of step-shaped grooves spaced apart from each other in the gate contact region of the gate stack and defined at different depths in the gate stack;
a plurality of openings passing through the dummy stack and spaced apart from each other;
a first gap-fill insulating pattern ng the plurality of step-shaped grooves;
a second gap-fill insulating pattern filling the plurality of openings;
a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns; and
a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.