US 12,170,332 B2
Fin field effect transistor devices including NMOS device and PMOS device with varied geometry of work function layers
Yuan-Sheng Huang, Taichung (TW); and Ryan Chia-Jen Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 21, 2023, as Appl. No. 18/356,256.
Application 18/356,256 is a continuation of application No. 17/716,976, filed on Apr. 8, 2022, granted, now 11,804,548.
Application 17/716,976 is a continuation of application No. 16/990,946, filed on Aug. 11, 2020, granted, now 11,302,816, issued on Apr. 12, 2022.
Prior Publication US 2023/0369493 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/823431 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first device, comprising:
a plurality of first fins;
a first work function layer over the plurality of first fins, wherein a portion of the first work function layer is located between the plurality of first fins; and
a first contact layer over the first work function layer; and
a second device, comprising:
a plurality of second fins;
a second work function layer and the first work function layer over the plurality of second fins, wherein a portion of the first work function layer and a portion of the second work function layer are located between the plurality of second fins; and
a second contact layer over the first work function layer and the second work function layer,
wherein a distance between a bottom surface of the first work function layer of the first device and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.