US 12,169,468 B2
Inter-integrated circuit sound (I2S) serial bus interface with support for multiple sample rates
Shi-Jie Li, Sichuan (CN)
Assigned to Synaptics Incorporated, San Jose, CA (US)
Filed by Synaptics Incorporated, San Jose, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 18/051,991.
Prior Publication US 2024/0143537 A1, May 2, 2024
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4282 (2013.01) 18 Claims
OG exemplary drawing
 
1. A method of communicating audio data by a serial bus interface, comprising:
outputting a first word select (WS) signal based on direct digital synthesis (DDS) of a clock signal using a frequency control word, the first WS signal periodically transitioning between a low logic state and a high logic state based on the clock signal having a first frequency so that each transition of the first WS signal is aligned with a respective edge of the clock signal;
biasing the frequency control word so that the first WS signal transitions from the low logic state to the high logic state at a desired frequency over a threshold duration, the first frequency being a non-integer multiple of the desired frequency; and
outputting a series of data frames associated with the first WS signal, over a serial bus, for at least the threshold duration.