US 12,169,670 B2
Systems and methods for designing a module semiconductor product
James Joseph Victory, Trabuco Canyon, CA (US); Klaus Neumaier, Erding (DE); YunPeng Xiao, Shanghai (CN); Jonathan Harper, Munich (DE); Vaclav Valenta, Brno (CZ); Stanley Benczkowski, Bear Creek Township, PA (US); Thierry Bordignon, Toulouse (FR); and Wai Lun Chu, Kowloon (HK)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Oct. 2, 2023, as Appl. No. 18/479,179.
Application 18/479,179 is a continuation of application No. 17/930,081, filed on Sep. 7, 2022, granted, now 11,816,405.
Application 17/930,081 is a continuation of application No. 17/076,072, filed on Oct. 21, 2020, granted, now 11,481,533, issued on Oct. 25, 2022.
Claims priority of provisional application 62/923,615, filed on Oct. 21, 2019.
Prior Publication US 2024/0028801 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/31 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01); G06F 111/02 (2020.01); G06F 117/12 (2020.01); G06F 119/08 (2020.01)
CPC G06F 30/31 (2020.01) [G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01); G06F 2111/02 (2020.01); G06F 2117/12 (2020.01); G06F 2119/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system configured for designing a multi-chip module, the system comprising:
one or more hardware processors configured by machine-readable instructions to:
receive a selection of a multi-chip module type and a selection of two or more die from a user;
generate a module configuration file;
generate a module bonding diagram;
select one or more SPICE models corresponding with the two or more die;
provide the module configuration file, the module bonding diagram, and the one or more SPICE models to a three dimensional simulation module;
generate a product SPICE model that includes module packaging;
generate a three dimensional model for the multi-chip module using the three dimensional simulation module; and
provide access to at least the module bonding diagram, the product SPICE model including module packaging, and the three dimensional model to the user.