US 12,169,459 B2
Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation
Arnav Goel, Palo Alto, CA (US); Neal Sanghvi, Palo Alto, CA (US); Jiayu Bai, Palo Alto, CA (US); Qi Zheng, Palo Alto, CA (US); and Ravinder Kumar, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,021.
Prior Publication US 2024/0248853 A1, Jul. 25, 2024
Int. Cl. G06F 12/1009 (2016.01); G06F 12/10 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/10 (2013.01); G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A heterogeneous processing system, comprising:
a host processor;
a first processor coupled to a first memory, wherein the first processor comprises a reconfigurable processor that includes:
an array of coarse-grained reconfigurable units comprising, an address generation unit, a plurality of memory units, and a plurality of compute units interconnected by an array-level network;
a top-level network coupled to the address generation unit of the array of coarse-grained reconfigurable units; and
an interface coupled between the top-level network and an external port of the first processor;
a second processor coupled to a second memory; and
switch and bus circuitry that communicatively couples the host processor, the external port of the first processor, and the second processor;
wherein the host processor is programmed to configure the address generation unit of the array of coarse-grained reconfigurable unit in the first processor to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry so that the first processor can directly access the second memory using the mapped physical addresses according to memory extension operation.