US 12,169,443 B2
Parallel processing system runtime state reload
Daniel William Bailey, Austin, TX (US); and David Glasco, Austin, TX (US)
Assigned to Tesla, Inc., Austin, TX (US)
Filed by Tesla, Inc., Austin, TX (US)
Filed on Dec. 5, 2022, as Appl. No. 18/061,620.
Application 18/061,620 is a continuation of application No. 17/066,288, filed on Oct. 8, 2020, granted, now 11,526,409.
Application 17/066,288 is a continuation of application No. 15/979,771, filed on May 15, 2018, granted, now 10,802,929, issued on Oct. 13, 2020.
Claims priority of provisional application 62/613,306, filed on Jan. 3, 2018.
Prior Publication US 2023/0102197 A1, Mar. 30, 2023
Int. Cl. G06F 11/18 (2006.01); G06F 9/52 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 11/267 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/1469 (2013.01) [G06F 9/52 (2013.01); G06F 11/0724 (2013.01); G06F 11/0796 (2013.01); G06F 11/1629 (2013.01); G06F 11/1658 (2013.01); G06F 11/181 (2013.01); G06F 11/183 (2013.01); G06F 11/2028 (2013.01); G06F 11/267 (2013.01); G06F 11/3013 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A parallel processing system comprising:
at least three processors configured for parallel operation, wherein the processors are included in a vehicle; and
state monitoring circuitry coupled to the processors, the state monitoring circuitry being configured to monitor a plurality of pipeline stages of individual processors included in a subset of the plurality of processors, wherein the state monitoring circuitry is configured to:
identify a first processor of the plurality of processors having at least one runtime state error associated with at least one pipeline stage, wherein identifying the first processor is based on comparing runtime states of the processors; and
state reload circuitry coupled to the processors, the state reload circuitry configured to update the runtime state of the at least one pipeline stage of the first processor based on one or more remaining processors of the subset, wherein the state reload circuitry is configured to adjust a voltage or common clock for the subset.