CPC H01L 21/0262 (2013.01) [C30B 25/04 (2013.01); C30B 29/403 (2013.01); C30B 29/406 (2013.01); H01L 21/02389 (2013.01); H01L 21/02433 (2013.01); H01L 21/02458 (2013.01); H01L 21/02494 (2013.01); H01L 21/0254 (2013.01); H01L 21/02639 (2013.01); H01L 21/02642 (2013.01); H01L 21/02647 (2013.01); H01L 21/0337 (2013.01)] | 10 Claims |
1. A method for manufacturing a plurality of semiconductor devices each including a crystal growth-derived layer and a semiconductor layer, the method comprising:
preparing a crystal growth-derived-layer forming substrate including (a) a substrate having a first growth region and a second growth region defined by a non-growth region having a striped configuration, (b) a first crystal growth-derived layer located above the first growth region and the non-growth region, and (c) a second crystal growth-derived layer located above the second growth region and the non-growth region; and
growing a first semiconductor layer on the first crystal growth-derived layer and growing a second semiconductor layer on the second crystal growth-derived layer, wherein:
the first semiconductor layer and the second semiconductor layer are separated from each other and are adjacent to each other, and the first crystal growth-derived layer and the second crystal growth-derived layer are separated from each other,
each of the first crystal growth-derived layer and the second crystal growth-derived layer has a lower portion joined to the substrate,
the lower portion has a width that gradually increases with distance from the substrate,
each of the first crystal growth-derived layer and the second crystal growth-derived layer includes a nitride semiconductor, and
a longitudinal direction of the striped configuration is aligned with a direction of an m-axis of both the first crystal growth-derived layer and the second crystal growth-derived layer.
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