US 12,170,127 B2
Buffer configurations for communications between memory dies and a host device
Sujeet V. Ayyapureddi, Boise, ID (US); Brent Keeth, Boise, ID (US); and Matthew A. Prather, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 22, 2022, as Appl. No. 18/086,991.
Claims priority of provisional application 63/266,091, filed on Dec. 28, 2021.
Prior Publication US 2023/0206969 A1, Jun. 29, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 5/04 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 7/1084 (2013.01); G11C 7/222 (2013.01); G11C 5/04 (2013.01); G11C 7/1057 (2013.01); G11C 2207/101 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a buffer comprising a first interface and a second interface, the first interface configured to be coupled with a host device and the second interface configured to be coupled with one or more memory dies, the buffer configured to:
receive, at the first interface and from the host device, data communicated at a first frequency and according to a first signaling scheme comprising a first quantity of voltage levels; and
output, from the second interface to a memory die of the one or more memory dies, the data at a second frequency lower than the first frequency and according to a second signaling scheme comprising a second quantity of voltage levels, wherein the second quantity of voltage levels is greater than the first quantity of voltage levels.