CPC H04B 10/60 (2013.01) [H03L 7/0807 (2013.01)] | 4 Claims |
1. An optical receiver chip based on OTN transmission technology, characterized in that, comprising:
a receiver RX, a digital control unit DIGIITAL and a power module POWER;
the digital control unit DIGIITAL is arranged to provide a control signal to the receiver RX;
the power module POWER is arranged to provide working power for the chip;
the receiver RX comprises a 28G transimpedance amplifier 28G_TIA and a limiting amplifier LA, wherein the limiting amplifier LA comprises a linear equalizer CTLE an optical modulation amplitude loss of signal module OMA LOS, a received signal strength indicator module RSSI LOS, a multi-rate clock data recovery module CDR, a signal bypass ByPass, and a fiber channel mode rate decision module FC_mode_Rate_decision, a data selector MUX, a monitor clock MONITOR CLOCK and an output buffer CML_BUFF,
an input terminal of the 28G transimpedance amplifier 28G_TIA is connected to a positive terminal of the photodiode PD through a chip pin PINA, a negative terminal of the photodiode PD is connected to a chip pin PINK,
two output terminals of the 28G transimpedance amplifier 28G_TIA are respectively connected to two input terminals of the linear equalizer CTLE and two input terminals of the optical modulation amplitude loss of signal module OMA LOS,
the 28G transimpedance amplifier 28G_TIA outflow RSSI monitoring current to received signal strength indicator module RSSI LOS,
control signal output terminals of both the optical modulation amplitude loss of signal module OMA LOS and the received signal strength indicator module RSSI LOS are respectively connected to a control terminal of the linear equalizer CTLE, a control terminal of the output buffer CML BUFF and a chip pin RX LOS;
an output terminal of the linear equalizer CTLE is respectively connected to an input terminal of the multi-rate clock data recovery module CDR, an input terminal of the signal bypass ByPass and an input terminal of the fiber channel mode rate decision module FC_mode_Rate_decision;
a control signal of the fiber channel mode rate decision module FC mode Rate decision is output to one of a control port of the multi-rate clock data recovery module CDR and a control port of ByPass;
a data signal output terminal of multi-rate clock recovery module CDR is connected to an input terminal of the data selector MUX;
a data signal output terminal of the signal bypass ByPass is connected to another input terminal of the selector MUX;
an output terminal of the data selector MUX is connect to an input terminal of the output buffer CML BUFF;
a clock output terminal of the multi-rate clock data recovery module CDR is connected to an input terminal of the monitor clock module MONITOR CLOCK,
the positive and negative output terminals of the monitoring clock module MONITOR CLOCK are respectively connected chip pins MCLKP and MCLKN;
two output terminals of the output buffer CML BUFF are respectively connected to chip pins OUTP and OUTN;
wherein the 28G transimpedance amplifier 28G_TIA converts a received weak optical signal into an electrical signal and amplifies the signal, and in a next-stage, a limiting amplifier LA further amplifies the electrical signal to a limiting state and outputs the signal, then the signal is determined to have a signal strength which meets the protocol requirements or a present threshold requirements by (a) or (b) respectively,
wherein in (a), a negative terminal of a photodiode PD outputs a high-frequency weak current, and processes low-pass filtering and mirroring into a DC current RSSI, which is then processed by an internal received signal strength indicator module RSSI LOS of the limiting amplifier LA to judge whether the signal meets the protocol requirements,
if the protocol requirements are not met, the output buffer CML BUFF and the linear equalizer CTLE inside the limiting amplifier LA are turned off, and a judgment result that the protocol requirements are not met is transmitted to the host computer outside the chip simultaneously;
wherein in (b), the optical modulation amplitude loss of signal module OMA LOS of the internal module of the limiting amplifier LA is arranged to judge whether the amplified electrical signal output by the 28G transimpedance amplifier 28G_TIA meets a preset threshold requirements,
if the preset threshold requirements are not met, the output buffer CML_BUFF and the linear equalizer CTLE inside the limiting amplifier LA are turned off, and the judgment result is transmitted to the host computer outside the chip simultaneously.
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