US 12,170,111 B2
Nonvolatile memory device including selection transistors and operating method thereof
Hyung Jin Choi, Gyeonggi-do (KR); and Chan Hui Jeong, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 31, 2023, as Appl. No. 18/103,496.
Claims priority of application No. 10-2022-0127646 (KR), filed on Oct. 6, 2022.
Prior Publication US 2024/0120008 A1, Apr. 11, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 16/0483 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An operating method of a non-volatile memory device, the operating method comprising:
simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines;
sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and
sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.