US 12,170,126 B2
Stacked DRAM device and method of manufacture
Thomas Vogelsang, Mountain View, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jan. 23, 2024, as Appl. No. 18/420,688.
Application 18/420,688 is a continuation of application No. 17/568,649, filed on Jan. 4, 2022, granted, now 11,894,093.
Application 17/568,649 is a continuation of application No. 17/135,138, filed on Dec. 28, 2020, granted, now 11,227,639, issued on Jan. 18, 2022.
Application 17/135,138 is a continuation of application No. 16/801,990, filed on Feb. 26, 2020, granted, now 10,885,946, issued on Jan. 5, 2021.
Application 16/801,990 is a continuation of application No. 16/256,887, filed on Jan. 24, 2019, granted, now 10,614,859, issued on Apr. 7, 2020.
Application 16/256,887 is a continuation of application No. 15/603,333, filed on May 23, 2017, granted, now 10,204,662, issued on Feb. 12, 2019.
Application 15/603,333 is a continuation of application No. 14/114,725, granted, now 9,666,238, issued on May 30, 2017, previously published as PCT/US2012/037664, filed on May 11, 2012.
Claims priority of provisional application 61/485,359, filed on May 12, 2011.
Prior Publication US 2024/0242741 A1, Jul. 18, 2024
Int. Cl. G11C 5/06 (2006.01); G11C 5/02 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01)
CPC G11C 5/063 (2013.01) [G11C 5/025 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H10B 12/50 (2023.02); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first integrated circuit (IC) memory chip including
first memory core circuitry,
a first interface circuit decoupled from the first memory core circuitry, and
a first transfer circuit to transfer first data between a first number of core data paths of the first memory core circuitry and a second number of data paths coupled to at least one through-silicon-via (TSV), the second number of data paths being less than the first number of core data paths;
a second IC memory chip vertically stacked with the first IC memory chip, the second IC memory chip including
second memory core circuitry,
a second interface circuit coupled to the second memory core circuitry for transferring second data with a memory controller, the second interface circuit coupled to the at least one TSV for transferring the first data between the multiple core data paths of the first memory core circuitry and the memory controller.