CPC G06F 13/1668 (2013.01) [G06F 1/266 (2013.01)] | 20 Claims |
1. A memory system, comprising:
one or more memory devices comprising one or more drivers;
a pin coupled with the one or more memory devices and configured to receive a chip enable signal for the one or more memory devices; and
one or more controllers coupled with the one or more memory devices and the pin, wherein the one or more controllers are configured to cause the memory system to:
bias the pin to a first voltage, the first voltage corresponding to a first status of the one or more memory devices, the first status indicating that the one or more memory devices are accessible;
bias the pin to a second voltage, the second voltage corresponding to a second status of the one or more memory devices, the second status indicating that the one or more memory devices are inaccessible; and
determine the first status, the second status, or both of the one or more memory devices based at least in part on comparing the first voltage and the second voltage to a set of voltages associated with statuses of the one or more memory devices.
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