CPC H01L 22/12 (2013.01) [H01L 29/401 (2013.01); H01L 29/4236 (2013.01)] | 14 Claims |
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming multiple gate trenches arranged at intervals on the base; wherein the multiple gate trenches comprise a plurality of first gate trenches and a plurality of second gate trenches, the plurality of first gate trenches and the plurality of second gate trenches are arranged alternately along a first direction, and a width of each of the first gate trenches is different from a width of each of the second gate trenches; and
forming a gate structure in each of the gate trenches, wherein each gate structure comprises a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of conductive layers comprises polysilicon.
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