US 12,170,321 B2
Fin field effect transistor having conformal and non-conformal gate dielectric layers
Kuei-Lun Lin, Keelung (TW); Yen-Fu Chen, Hsinchu (TW); Po-Ting Lin, Hsinchu (TW); Chia-Yuan Chang, Hsinchu (TW); Xiong-Fei Yu, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 11, 2020, as Appl. No. 17/018,031.
Claims priority of provisional application 62/927,330, filed on Oct. 29, 2019.
Prior Publication US 2021/0126101 A1, Apr. 29, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/42368 (2013.01) [H01L 21/28194 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/7856 (2013.01); H01L 29/513 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a fin extending from a substrate;
forming a sacrificial layer along a top surface and sidewalls of the fin;
removing the sacrificial layer to form an opening, the opening exposing the fin; and
forming a gate dielectric layer along the top surface and the sidewalls of the fin, wherein a first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin, and wherein forming the gate dielectric layer comprises:
implementing a cycle of:
performing a conformal deposition process on the top surface and the sidewalls of the fin; and
after the conformal deposition process, performing a non-conformal deposition process on the top surface and the sidewalls of the fin; and
repeating the cycle one or more times.