CPC H10B 99/00 (2023.02) [H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 29/7869 (2013.01)] | 20 Claims |
1. A method, comprising:
forming multiple memory stacks stacked over one another and stacked over a semiconductor substrate;
performing an etch to pattern the memory stacks into multiple columns of memory stack structures, wherein read bitline (RBL) trenches and write wordline (WWL) trenches are on opposite sides of the multiple columns of memory stack structures to separate the multiple columns of memory stack structures from one another;
performing a first lateral etch to remove outermost conductive regions from each memory stack structure, thereby forming first recesses in sidewalls of each memory stack structure; and
filling the RBL trenches, the WWL trenches, and the first recesses with a dielectric material; and
re-opening the RBL trenches while leaving the WWL trenches filled with the dielectric material.
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