US 12,170,200 B2
Crystal growth method and a substrate for a semiconductor device
Takehiro Nishimura, Kusatsu (JP); and Chiaki Doumoto, Goleta, CA (US)
Assigned to KYOCERA Corporation, Kyoto (JP)
Filed by KYOCERA Corporation, Kyoto (JP)
Filed on Dec. 30, 2021, as Appl. No. 17/565,831.
Application 17/565,831 is a continuation of application No. 16/254,031, filed on Jan. 22, 2019, granted, now 11,244,826.
Claims priority of application No. 2018-015982 (JP), filed on Jan. 31, 2018.
Prior Publication US 2022/0122839 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); C30B 25/04 (2006.01); C30B 29/40 (2006.01); H01L 21/033 (2006.01)
CPC H01L 21/0262 (2013.01) [C30B 25/04 (2013.01); C30B 29/403 (2013.01); C30B 29/406 (2013.01); H01L 21/02389 (2013.01); H01L 21/02433 (2013.01); H01L 21/02458 (2013.01); H01L 21/02494 (2013.01); H01L 21/0254 (2013.01); H01L 21/02639 (2013.01); H01L 21/02642 (2013.01); H01L 21/02647 (2013.01); H01L 21/0337 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for manufacturing a plurality of semiconductor devices each including a crystal growth-derived layer and a semiconductor layer, the method comprising:
preparing a crystal growth-derived-layer forming substrate including (a) a substrate having a first growth region and a second growth region defined by a non-growth region having a striped configuration, (b) a first crystal growth-derived layer located above the first growth region and the non-growth region, and (c) a second crystal growth-derived layer located above the second growth region and the non-growth region; and
growing a first semiconductor layer on the first crystal growth-derived layer and growing a second semiconductor layer on the second crystal growth-derived layer, wherein:
the first semiconductor layer and the second semiconductor layer are separated from each other and are adjacent to each other, and the first crystal growth-derived layer and the second crystal growth-derived layer are separated from each other,
each of the first crystal growth-derived layer and the second crystal growth-derived layer has a lower portion joined to the substrate,
the lower portion has a width that gradually increases with distance from the substrate,
each of the first crystal growth-derived layer and the second crystal growth-derived layer includes a nitride semiconductor, and
a longitudinal direction of the striped configuration is aligned with a direction of an m-axis of both the first crystal growth-derived layer and the second crystal growth-derived layer.