US 12,170,249 B2
Semiconductor package including interposer
Jong-youn Kim, Seoul (KR); and Seok-hyun Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 9, 2023, as Appl. No. 18/332,494.
Application 18/332,494 is a continuation of application No. 17/743,805, filed on May 13, 2022, granted, now 11,710,701.
Application 17/743,805 is a continuation of application No. 17/100,171, filed on Nov. 20, 2020, granted, now 11,355,440, issued on Jun. 7, 2022.
Application 17/100,171 is a continuation of application No. 16/299,340, filed on Mar. 12, 2019, granted, now 10,847,468, issued on Nov. 24, 2020.
Claims priority of application No. 10-2018-0089508 (KR), filed on Jul. 31, 2018.
Prior Publication US 2023/0317623 A1, Oct. 5, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/5385 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3675 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lower redistribution structure comprising a plurality of lower insulating layers and a plurality of lower redistribution line patterns respectively on at least one of top surfaces and bottom surfaces of the plurality of lower insulating layers;
a plurality of first connection pillars on the lower redistribution structure;
an interposer apart from the plurality of first connection pillars on the lower redistribution structure and comprising an interposer substrate, a plurality of connection wiring patterns on a top surface of the interposer substrate, and a through electrode interconnecting some others of the plurality of connection wiring patterns to the lower redistribution structure by penetrating the interposer substrate;
an upper redistribution structure electrically connected to the plurality of connection wiring patterns, the upper redistribution structure comprising at least one upper insulating layer and a plurality of upper redistribution line patterns on a top surface or a bottom surface of the at least one upper insulating layer and connected to the plurality of first connection pillars;
a filling insulating layer between the lower redistribution structure and the upper redistribution structure;
at least two semiconductor chips on the upper redistribution structure, electrically connected to the upper redistribution structure, and apart from each other; and
a molding member surrounding the at least two semiconductor chips on the upper redistribution structure,
wherein a thickness of the lower redistribution structure is greater than a thickness of the upper redistribution structure.