CPC G09G 3/2096 (2013.01) [G09G 3/3275 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/021 (2013.01); G09G 2370/10 (2013.01)] | 20 Claims |
1. A source driver Integrated Circuit (IC), comprising:
a reception circuit configured to receive an input data packet from a timing controller when operating in a normal mode and obtain an image data and a first clock signal from the input data packet;
a control circuit configured to receive and output the image data and the first clock signal from the reception circuit when operating in the normal mode, the control circuit configured to receive and output a second clock signal from the timing controller when operating in a low power mode; and
an output buffer circuit configured to output a data voltage related to the image data when operating in the normal mode and maintain an output of the data voltage when operating in the low power mode,
wherein the output buffer circuit is configured to output the data voltage according to the first clock signal when operating in the normal mode and output the data voltage according to the second clock signal when operating in the low power mode.
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