US 12,171,099 B2
Semiconductor memory device capable of connecting each of a plurality of cell strings to a source line through a discharge transistor and method of manufacturing the same
Nam Jae Lee, Icheon-si (KR); and Myoung Kwan Cho, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 8, 2021, as Appl. No. 17/497,313.
Claims priority of application No. 10-2021-0048648 (KR), filed on Apr. 14, 2021.
Prior Publication US 2022/0336488 A1, Oct. 20, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate with a complementary metal oxide semiconductor (CMOS) circuit;
a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked over the substrate in a vertical direction;
a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and
a plurality of conductive layers disposed over the gate stacked body; and
a bit line that is coupled to a second end of the channel structure, the bit line disposed between the substrate and the gate stacked body,
wherein each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.