US 12,169,454 B2
Reduce data traffic between cache and memory via data access of variable sizes
Steven Jeffrey Wallach, Dallas, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 28, 2021, as Appl. No. 17/563,985.
Application 17/563,985 is a continuation of application No. 16/183,661, filed on Nov. 7, 2018, granted, now 11,237,970.
Prior Publication US 2022/0121576 A1, Apr. 21, 2022
Int. Cl. G06F 12/0842 (2016.01)
CPC G06F 12/0842 (2013.01) [G06F 2212/1008 (2013.01); G06F 2212/608 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A computing device, comprising:
a processor configured to access data using memory addresses in an address space;
a first memory configured to store a block of data at a block of contiguous addresses in the address space; and
a second memory configured to cache, in response to the processor accessing a memory address in the address space and a determination that data stored in the first memory at the memory address is not already cached in the second memory, a first portion of the block of data identified by an item selection vector, wherein the item selection vector comprises a variable number of items.