US 12,170,326 B2
Three-dimensional device with vertical core and bundled wiring
Mark I. Gardner, Ceer Creek, TX (US); and H. Jim Fulford, Marianna, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Nov. 4, 2021, as Appl. No. 17/453,518.
Claims priority of provisional application 63/159,649, filed on Mar. 11, 2021.
Prior Publication US 2022/0293523 A1, Sep. 15, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 29/66666 (2013.01) [H01L 21/823487 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H01L 21/823885 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a buried power rail (BPR) formed over a top surface of a substrate, the substrate including an opposing bottom surface;
a semiconductor structure formed over the BPR, the semiconductor structure being tube-shaped and extending along a vertical direction perpendicular to the substrate, the semiconductor structure further including a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region;
a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region of the semiconductor structure;
a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region such that the gate electrode is surrounded by the gate region; and
a second S/D interconnect structure positioned over and coupled to the second S/D region.