US 12,170,258 B2
Memory devices having vertical transistors and methods for forming the same
Simon Shi-Ning Yang, Wuhan (CN); Hongbin Zhu, Wuhan (CN); Wei Liu, Wuhan (CN); and Wenyu Hua, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 16, 2021, as Appl. No. 17/553,789.
Application 17/553,789 is a continuation of application No. PCT/CN2021/122022, filed on Aug. 30, 2021.
Claims priority of application No. PCT/CN2021/115545 (WO), filed on Aug. 31, 2021; application No. PCT/CN2021/115594 (WO), filed on Aug. 31, 2021; application No. PCT/CN2021/115652 (WO), filed on Aug. 31, 2021; application No. PCT/CN2021/115704 (WO), filed on Aug. 31, 2021; application No. PCT/CN2021/115743 (WO), filed on Aug. 31, 2021; application No. PCT/CN2021/115775 (WO), filed on Aug. 31, 2021; and application No. PCT/CN2021/115820 (WO), filed on Aug. 31, 2021.
Prior Publication US 2023/0069096 A1, Mar. 2, 2023
Int. Cl. H01L 27/108 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a semiconductor layer extending in a lateral plane;
a peripheral circuit comprising a peripheral transistor in contact with the semiconductor layer;
an array of memory cells disposed on a lateral side of the semiconductor layer and the peripheral circuit, wherein each of the memory cells comprises a vertical transistor extending in a first direction perpendicular to the lateral plane, and a storage unit coupled to the vertical transistor, the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with one or more lateral sides of the semiconductor body, and the semiconductor body is aligned with the semiconductor layer in the lateral plane; and
bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.