US 12,170,107 B2
Self-refresh state with decreased power consumption
Shawn M. Hilde, Meridian, ID (US); Dennis G. Montierth, Meridian, ID (US); and Garth N. Grubb, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 24, 2022, as Appl. No. 17/808,818.
Prior Publication US 2023/0420023 A1, Dec. 28, 2023
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40615 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of rows of memory cells;
a refresh circuit coupled with the plurality of rows of memory cells and configured to:
enter a self-refresh state to refresh the plurality of rows of memory cells; and
execute, based at least in part on entering the self-refresh state, a plurality of first refresh operations on the plurality of rows of memory cells according to a first rate for executing refresh operations; and
a refresh rate circuit coupled with the plurality of rows of memory cells and the refresh circuit, the refresh rate circuit configured to:
determine, while the apparatus is in the self-refresh state, whether to decrease a rate for executing refresh operations in the self-refresh state from the first rate to a second rate based at least in part on whether each row of the plurality of rows of memory cells is refreshed according to the first rate,
wherein the refresh circuit is further configured to execute a plurality of second refresh operations on the plurality of rows of memory cells according to the second rate based at least in part on determining whether to decrease the rate.