CPC H10B 10/18 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H10B 10/12 (2023.02)] | 20 Claims |
1. A circuit layout comprising:
a first layout circuit comprising:
a first n-type transistor and a second n-type transistor disposed in a first p-type doped region; and
a first p-type transistor and a second p-type transistor disposed in a first n-type doped region,
wherein the first n-type doped region is disposed immediately adjacent to the first p-type doped region in a first direction;
a second layout circuit diagonally located with respect to the first layout circuit, the second layout circuit comprising:
third and fourth p-type transistors disposed in a second n-type doped region,
wherein the second n-type doped region is diagonally arranged with the first n-type doped region; and
third and fourth n-type transistors disposed in a second p-type doped region,
wherein the second p-type doped region is immediately adjacent to the second n-type doped region,
wherein the second n-type doped region is diagonal to the first n-type doped region, and
wherein there is no transitional space between the second n-type doped region and the first n-type doped region.
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