CPC H01L 27/0886 (2013.01) [H01L 21/02205 (2013.01); H01L 21/02211 (2013.01); H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/42372 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 21/31053 (2013.01); H01L 29/517 (2013.01); H01L 29/7848 (2013.01)] | 20 Claims |
1. A method of manufacturing a gate structure, comprising:
forming a gate dielectric layer;
depositing a work function layer on the gate dielectric layer;
forming a barrier layer on the work function layer, comprising:
forming a first TiN layer on the work function layer;
converting a top portion of the first TiN layer into a trapping layer, wherein the trapping layer comprises silicon atoms or aluminum atoms; and
forming a second TiN layer on the trapping layer; and
depositing a metal layer on the barrier layer to introduce fluorine atoms into the barrier layer.
|