CPC H03M 13/1131 (2013.01) [H03M 13/1125 (2013.01); H03M 13/3961 (2013.01)] | 12 Claims |
1. A radio receiver device, comprising:
at least one processor; and
at least one memory storing instructions that, when executed by the at least one processor, cause the radio receiver device at least to perform:
receiving a radio signal comprising low-density parity-check, LDPC, encoded information bits; and
applying LDPC decoding to the received LDPC encoded information bits to recover the information bits, the applying of the LDPC decoding comprising processing an LDPC base graph,
wherein the processing of the LDPC base graph comprises scheduling a processing of at least one sequence of rows of the LDPC base graph according to a scheduling state of the at least one sequence of rows, such that transitioning from a current scheduling state of the at least one sequence of rows to a subsequent scheduling state of the at least one sequence of rows occurs according to a state transition metric.
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