CPC H01L 23/5226 (2013.01) [H01L 21/76816 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 23/5283 (2013.01); H01L 27/0886 (2013.01)] | 20 Claims |
1. A method, comprising:
providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers;
depositing a first dielectric layer over the MG and the gate spacers;
depositing a first metal layer over the S/D feature, the first metal layer comprising a top portion and a bottom portion;
removing the top portion of the first metal layer to form a trench, wherein a top surface of the bottom portion of the first metal layer is a bottom surface of the trench, and a top portion of sidewalls of the gate spacers forms one of sidewalls of the trench;
depositing a second dielectric layer on the sidewalls of the trench to partially fill the trench, wherein the second dielectric layer directly contacts the bottom surface of the trench;
recessing the bottom portion of the first metal layer to extend the trench to below a bottommost surface of the second dielectric layer; and
depositing a second metal layer over the recessed bottom portion of the first metal layer and in the trench, wherein the second dielectric layer and the second metal layer completely fill the trench.
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