US 12,169,720 B2
System with dynamically selectable firmware image sequencing for production test, debug, prototyping
Nariankadu D. Hemkumar, Austin, TX (US); Christopher Jackson, Austin, TX (US); Younes Djadi, Austin, TX (US); and Nathan Daniel Pozniak Buchanan, Austin, TX (US)
Assigned to Cirrus Logic, Inc., Austin, TX (US)
Filed by Cirrus Logic International Semiconductor Ltd., Edinburgh (GB)
Filed on Sep. 30, 2022, as Appl. No. 17/957,708.
Application 17/957,708 is a continuation in part of application No. 17/472,196, filed on Sep. 10, 2021, granted, now 11,899,567.
Prior Publication US 2023/0080059 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/4401 (2018.01); G06F 8/65 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/4401 (2013.01) [G06F 8/65 (2013.01); G06F 9/3802 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system comprising:
a memory programmed with multiple firmware images, wherein each firmware image of the multiple firmware images has an associated entry point that is distinct from the entry point of the other firmware images;
a processor that fetches instructions of the multiple firmware images from the memory and executes the fetched instructions;
a hardware register writable with an address; and
a controller that is external to the processor and that is configured to, with respect to each reset of a sequence of resets of the processor:
hold the processor in the reset;
read an entry point of one of the firmware images from the hardware register;
write the entry point to the processor; and
release the processor from the reset to cause the processor to fetch its first instruction out of the reset from the memory at the entry point read from the hardware register;
wherein the multiple firmware images comprise:
a boot firmware image;
a mission mode firmware image; and
at least one other firmware image.