US 12,170,116 B2
Operating method for a memory, a memory and a memory system
Boxuan Cheng, Hubei (CN); and Lu Guo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Dec. 28, 2022, as Appl. No. 18/090,104.
Claims priority of application No. 202211288018.7 (CN), filed on Oct. 20, 2022.
Prior Publication US 2024/0135998 A1, Apr. 25, 2024
Prior Publication US 2024/0233834 A9, Jul. 11, 2024
Int. Cl. G11C 16/28 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/28 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A memory, comprising:
a memory array comprising a memory plane having memory cells; and
a peripheral circuit coupled to the memory array, the peripheral circuit being configured to:
obtain at least one set of read voltages, each of the at least one set of read voltages comprising an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value, the initial voltage value in each of the at least one set of read voltages being a preset read voltage for distinguishing two adjacent memory states of one of the memory cells;
perform read operations respectively based on the initial voltage values and the offset voltage values in the at least one set of read voltages, and obtain a quantity of the memory cells in which a read result corresponding to each voltage value meets the set conditions;
determine a difference between the two quantities corresponding to every two adjacent voltage values belonging to a same set of read voltages; and
determine an optimal read voltage for distinguishing the two adjacent memory states based on the difference.