US 12,170,278 B2
Semiconductor device and layout design method
Jeong-Lim Kim, Seoul (KR); Myung Soo Noh, Suwon-si (KR); No Young Chung, Hwaseong-si (KR); Seok Yun Jeong, Osan-si (KR); and Young Han Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 14, 2022, as Appl. No. 18/080,832.
Application 18/080,832 is a division of application No. 16/837,101, filed on Apr. 1, 2020, granted, now 11,557,582.
Claims priority of application No. 10-2019-0108535 (KR), filed on Sep. 3, 2019.
Prior Publication US 2023/0109875 A1, Apr. 13, 2023
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 27/092 (2006.01); H10B 10/00 (2023.01); G06F 117/12 (2020.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); H01L 27/0924 (2013.01); H10B 10/12 (2023.02); G06F 2117/12 (2020.01)] 3 Claims
OG exemplary drawing
 
1. A layout design method comprising:
preparing an original layout, wherein the original layout comprises a first SRAM unit cell and a second SRAM unit cell;
searching for an original contact pattern which directly connects a first fin pattern of the first SRAM unit cell and a second fin pattern of the second SRAM unit cell;
generating a first contact pattern which directly contacts the first fin pattern and a second contact pattern which directly contacts the second fin pattern by cutting the original contact pattern;
generating a first target pattern and a second target pattern by reflecting etch skew in the first contact pattern and the second contact pattern; and
performing optical proximity correction (OPC) on the first target pattern and the second target pattern.