CPC G11C 11/1673 (2013.01) [G11C 11/005 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H10B 61/22 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a first MRAM cell array;
a memory cell select transistor having a first threshold configured to selectively apply a first write current to a selected one of a plurality of first MRAM bit cells in the first MRAM cell array to selectively write the selected one of the first MRAM bit cells to a parallel state or an anti-parallel state;
a first OTP select transistor having a second threshold lower than the first threshold configured to selectively apply a breakdown current higher than the first write current to a first OTP MRAM cell in the first MRAM cell array to write the first OTP MRAM cell to a breakdown state;
a second MRAM cell array;
a second OTP MRAM cell in the second array;
a second OTP select transistor connected to the second OTP MRAM cell, the second OTP select transistor configured to selectively apply a breakdown current to the second OTP MRAM cell, the second OTP select transistor configured to selectively apply the breakdown current to the second OTP MRAM cell to write the second OTP MRAM cell to a breakdown state; and
a memory controller configured to apply control signals to one of the first or second OTP select transistors, such that the first OTP MRAM cell is written to the breakdown state and the second OTP MRAM cell is not written to the breakdown state.
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