US 12,170,263 B2
Fabricating active-bridge-coupled GPU chiplets
Skyler J. Saleh, San Diego, CA (US); Ruijin Wu, San Diego, CA (US); Milind S. Bhagavat, Santa Clara, CA (US); and Rahul Agarwal, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 27, 2019, as Appl. No. 16/585,480.
Prior Publication US 2021/0098419 A1, Apr. 1, 2021
Int. Cl. H01L 23/00 (2006.01); G06F 8/41 (2018.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 21/60 (2006.01)
CPC H01L 24/96 (2013.01) [G06F 8/451 (2013.01); H01L 21/4846 (2013.01); H01L 21/563 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2021/6006 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/11002 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming active-bridge-coupled GPU chiplets, comprising:
bonding a first GPU chiplet and a second GPU chiplet to a temporary carrier wafer;
bonding a face surface of an active bridge chiplet to a face surface of the first and second GPU chiplets, wherein the active bridge chiplet includes a level of cache memory and wherein the active bridge chiplet is configured to communicatively couple the level of cache memory to the first and second GPU chiplets such that the level of cache memory is cache coherent across the first and second GPU chiplets; and
mounting the first and second GPU chiplets to a carrier substrate.