US 12,170,108 B2
Circuitry for power management assertion
Sanjeev Kumar Jain, Ottawa (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 30, 2023, as Appl. No. 18/325,170.
Application 18/325,170 is a continuation of application No. 17/468,771, filed on Sep. 8, 2021, granted, now 11,670,365.
Claims priority of provisional application 63/175,197, filed on Apr. 15, 2021.
Prior Publication US 2023/0298662 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A control circuit comprising:
a latch circuit configured to generate a first light sleep signal according to a sense amplifier enable signal and to provide the first light sleep signal to a bit line reading switch so the bit line reading switch is cutoff after a sense amplifier is enabled, wherein the latch circuit comprises a logic gate configured to compare the sense amplifier enable signal and a clock signal.