CPC G11C 7/222 (2013.01) [G11C 7/1048 (2013.01); G11C 7/109 (2013.01)] | 20 Claims |
1. A data receiving circuit, comprising:
a first amplification module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal respectively through a first node and a second node;
a decision feedback control module, configured to generate a second sampling clock signal in response to an enable signal;
a decision feedback equalization module, connected to the first node and the second node, wherein the decision feedback equalization module is configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and based on a feedback signal to adjust the first voltage signal and the second voltage signal, and stop performing the decision feedback equalization when the enable signal is in a second level value interval, the feedback signal being obtained based on previously received data; and
a second amplification module, configured to amplify a voltage difference between the first voltage signal and the second voltage signal, and output a first output signal and a second output signal respectively through a third node and a fourth node.
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