US 12,170,330 B2
Three dimensional vertically structured electronic devices
Adam Conway, Livermore, CA (US); Sara Elizabeth Harrison, Fremont, CA (US); Rebecca Nikolic, Oakland, CA (US); Qinghui Shao, Fremont, CA (US); and Lars Voss, Livermore, CA (US)
Assigned to Lawrence Livermore National Security, LLC, Livermore, CA (US)
Filed by Lawrence Livermore National Security, LLC, Livermore, CA (US)
Filed on Apr. 22, 2021, as Appl. No. 17/238,012.
Application 17/238,012 is a division of application No. 14/990,612, filed on Jan. 7, 2016, granted, now 11,018,253.
Prior Publication US 2021/0328057 A1, Oct. 21, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 29/0657 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66924 (2013.01); H01L 29/7788 (2013.01); H01L 29/7789 (2013.01); H01L 29/8083 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
at least one vertical transistor, comprising:
a substrate comprising a first semiconductor material;
an array of three dimensional (3D) structures above the substrate, wherein each 3D structure comprises the first semiconductor material;
a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, wherein the sidewall heterojunction layer comprises a second semiconductor material, wherein the first and second semiconductor materials have different bandgaps; and
an isolation region positioned between the 3D structures.