CPC H01L 29/7786 (2013.01) [H01L 29/045 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7787 (2013.01)] | 17 Claims |
1. A semiconductor device, comprising:
a silicon substrate;
a buffer layer of III-N semiconductor material over the silicon substrate, wherein:
the buffer layer includes a columnar region having a first thickness;
the buffer layer includes a transition region surrounding the columnar region; and
the buffer layer includes an inter-columnar region around the transition region, the inter-columnar region having a second thickness, the first thickness being greater than the second thickness; and
the buffer layer has a (0001) crystal orientation, wherein a c-plane of the III-N semiconductor material of the buffer layer is parallel to a boundary plane between the buffer layer and the silicon substrate, and wherein a top surface in the inter-columnar region has a higher portion of surfaces off of the c-plane than a top surface in the columnar region; and
a gallium nitride field effect transistor (GaN FET), including:
a barrier layer of III-N semiconductor material over the buffer layer, the barrier layer extending across the columnar region and the transition region; and
a gate of p-type III-N semiconductor material over the barrier layer, the gate extending over the columnar region and the transition region, wherein:
the gate has a first gate thickness over the columnar region and a second gate thickness over the transition region;
both the first gate thickness and the second gate thickness are thicker than twice a vertical range of the top surface in the columnar region; and
a difference between the first gate thickness and the second gate thickness is less than half the vertical range of the top surface in the columnar region.
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