US 12,169,640 B2
Read retry method for enhancing read performance and stability of 3D NAND memory
Guangchang Ye, Hubei (CN); Lu Guo, Hubei (CN); and Zhongchen Huo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Aug. 16, 2022, as Appl. No. 17/889,212.
Prior Publication US 2024/0061606 A1, Feb. 22, 2024
Int. Cl. G06F 11/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices configured to store data; and
a memory controller coupled to the one or more memory devices and configured to:
detect a failure of a read operation performed at a portion of the one or more memory devices;
determine a trigger portion closest to the portion of the one or more memory devices where the failure of read operation is detected, wherein the trigger portion is one or more memory blocks or one or more memory pages, and wherein the trigger portion is a designated portion on the memory system where sensing and storing a set of values of effectors is performed;
access the set of values of a set of effectors of the read operation associated with the trigger portion;
analyze the set of values that correspond to the set of effectors of the read operation;
select one or more read retry routines from a plurality of read retry routines based on the analyzing, wherein each of the plurality of read retry routines is associated with
a different effector from the set of effectors, and
an adjusted read voltage that corresponds to the different effector; and
perform the selected one or more read retry routines corresponding to each effector of the set of effectors of the read operation at the portion of the one or more memory devices using the adjusted read voltage corresponding to each effector of the set of effectors to negate the failure of the read operation.