US 12,171,091 B2
Multi-layer high-k gate dielectric structure
Chih-Yu Hsu, Hsinchu County (TW); Jian-Hao Chen, Hsinchu (TW); Chia-Wei Chen, Hsinchu (TW); Shan-Mei Liao, Hsinchu (TW); Hui-Chi Chen, Hsinchu County (TW); Yu-Chia Liang, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Kuei-Lun Lin, Hsinchu (TW); Kuo-Feng Yu, Hsinchu (TW); Feng-Cheng Yang, Hsinchu County (TW); and Yen-Ming Chen, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,593.
Application 18/446,593 is a division of application No. 17/884,442, filed on Aug. 9, 2022.
Application 17/884,442 is a division of application No. 17/036,418, filed on Sep. 29, 2020.
Claims priority of provisional application 63/003,011, filed on Mar. 31, 2020.
Prior Publication US 2023/0389256 A1, Nov. 30, 2023
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first gate dielectric layer over an active region, the first gate dielectric layer containing a first type of material, wherein the first type of material has a first peak concentration level;
forming a second gate dielectric layer over the first gate dielectric layer, the second gate dielectric layer containing a second type of material different from the first type of material, wherein the second type of material has a second peak concentration level less than the first peak concentration level;
forming a third gate dielectric layer over the second gate dielectric layer, the third gate dielectric layer containing a third type of material different from the second type of material, wherein the third type of material has a third peak concentration level less than the second peak concentration level; and
forming a metal-containing gate electrode over the third gate dielectric layer.
 
11. A method, comprising:
depositing a first gate dielectric layer directly on a surface of an interfacial layer, wherein the first gate dielectric layer has a first material composition and a first thickness;
depositing a second gate dielectric layer directly on a surface of the first gate dielectric layer, wherein the second gate dielectric layer has a second material composition different from the first material composition, and wherein the second gate dielectric layer has a second thickness different from the first thickness;
depositing a third gate dielectric layer directly on a surface of the second gate dielectric layer, wherein the third gate dielectric layer has a third material composition different from the second material composition and the first material composition, and wherein the third gate dielectric layer has a third thickness different from the second thickness and the first thickness; and
forming a metal-containing gate electrode directly on a surface of the third gate dielectric layer;
wherein the depositing the first gate dielectric layer, the depositing the second gate dielectric layer, and the depositing the third gate dielectric layer are performed such that a first peak concentration level of the first material composition is greater than a second peak concentration level of the second material composition, and the second peak concentration level of the second material composition is greater than a third peak concentration level of the third material composition.
 
17. A method, comprising:
depositing a first gate dielectric layer over an upwardly protruding fin structure, wherein the first gate dielectric layer contains hafnium oxide;
depositing a second gate dielectric layer directly on an upwardly-facing upper surface and laterally-facing side surfaces of the first gate dielectric layer, wherein the second gate dielectric layer contains zirconium oxide;
depositing a third gate dielectric layer directly on an upwardly-facing upper surface and laterally-facing side surfaces of the second gate dielectric layer, wherein the third gate dielectric layer contains lanthanum oxide or aluminum oxide; and
depositing a metal-containing gate electrode directly on an upwardly-facing upper surface and laterally-facing side surfaces of the third gate dielectric layer.