US 12,169,675 B2
Automatic generation of layouts for analog integrated circuits
Yu-Tao Yang, Zhubei (TW); Wen-Shen Chou, Zhubei (TW); Yung-Chow Peng, Hsinchu (TW); and Yung-Hsu Chuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,574.
Application 18/362,574 is a division of application No. 17/212,728, filed on Mar. 25, 2021, granted, now 11,763,060.
Prior Publication US 2024/0028810 A1, Jan. 25, 2024
Int. Cl. G06F 30/39 (2020.01); G06F 11/32 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 11/324 (2013.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a processing device, device specifications for an analog integrated circuit;
generating, by the processing device, a non-final layout of the analog integrated circuit based on the device specifications, wherein generating the non-final layout comprises:
determining, by the processing device, an allowable spacing between a first cell of a first cell type and a second cell of a second cell type immediately adjacent the first cell,
wherein the determining the allowable spacing between the first cell of the first cell type and the second cell of the second cell type comprises:
generating, by the processing device, the non-final layout for the first cell;
placing, by the processing device, the second cell in the non-final layout;
performing design rule checking on the non-final layout:
determining, by the processing device, whether a spacing between the first cell and the second cell passes the design rule checking;
incrementing, by the processing device, the spacing between the first cell and the second cell if the spacing fails the design rule checking; and
repeating the performing the design rule checking on the non-final layout, the determining whether the spacing between the first cell and the second cell passes the design rule checking, and the incrementing the spacing between the first cell and the second cell if the spacing fails the design rule checking until the spacing passes the design rule checking;
partitioning, by the processing device, the non-final layout into a plurality of sub-cells;
performing, by the processing device, a quality control check on each sub-cell in the plurality of sub-cells to produce verified sub-cells;
merging, by the processing device, the verified sub-cells to form a merged layout of the analog integrated circuit; and
performing, by the processing device, a quality control check on the merged layout to produce a verified merged layout.