US 12,170,319 B2
Dual contact process with stacked metal layers
Kevin Cook, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Gilbert Dewey, Beaverton, OR (US); Nazila Haratipour, Hillsboro, OR (US); Ralph Thomas Troeger, Portland, OR (US); Christopher J. Jezewski, Portland, OR (US); and I-Cheng Tung, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,362.
Prior Publication US 2022/0102510 A1, Mar. 31, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41791 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A complementary metal-oxide-semiconductor (CMOS) device, comprising:
a first transistor with a first conductivity type, wherein the first transistor comprises:
a first source region and a first drain region; and
a first metal over and in contact with the first source region and the first drain region; and
a second transistor with a second conductivity type opposite from the first conductivity type, wherein the second transistor comprises:
a second source region and a second drain region;
a second metal over and in contact with the second source region and the second drain region; and
the first metal over and in contact with the second metal, the first metal different than the second metal, and the first metal in contact with the second source region and the second drain region.