US 12,170,251 B2
Semiconductor package
Kyoung Lim Suk, Suwon-si (KR); Seokhyun Lee, Hwaseong-si (KR); and Jaegwon Jang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 11, 2021, as Appl. No. 17/317,368.
Claims priority of application No. 10-2020-0125174 (KR), filed on Sep. 25, 2020.
Prior Publication US 2022/0102282 A1, Mar. 31, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 25/105 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2224/24265 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19104 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution substrate comprising:
a plurality of dielectric layers vertically stacked;
a plurality of redistribution patterns in each of the plurality of dielectric layers;
a first trench that extends through a top surface of the redistribution substrate,
wherein the first trench has a bottom surface that corresponds to a top surface of one of the plurality of dielectric layers, and an inner wall that corresponds to lateral surfaces of two or more of the plurality of dielectric layers; and
a plurality of dummy redistribution patterns in the first trench;
a first semiconductor chip on the redistribution substrate;
a capacitor chip on a bottom surface of the first semiconductor chip; and
an under-fill layer on the bottom surface of the first semiconductor chip,
wherein the plurality of dummy redistribution patterns vertically overlap the first semiconductor chip,
wherein an uppermost surface of each of the plurality of dummy redistribution patterns is at a level higher than a level of a bottom surface of the first trench, and
wherein the dummy redistribution patterns are not electrically connected to the first semiconductor chip and are not electrically connected to the capacitor chip.