US 12,171,092 B2
Layout of static random access memory periphery circuit
Yangsyu Lin, New Taipei (TW); Chi-Lung Lee, New Taipei (TW); Chien Chi Tien, Hsinchu (TW); and Chiting Cheng, Taiching (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor MAnufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 9, 2023, as Appl. No. 18/506,122.
Application 18/506,122 is a continuation of application No. 17/751,426, filed on May 23, 2022, granted, now 11,856,747.
Application 17/751,426 is a continuation of application No. 17/080,617, filed on Oct. 26, 2020, granted, now 11,342,340, issued on May 24, 2022.
Application 17/080,617 is a continuation of application No. 16/502,790, filed on Jul. 3, 2019, granted, now 10,818,677, issued on Oct. 27, 2020.
Claims priority of provisional application 62/715,529, filed on Aug. 7, 2018.
Claims priority of provisional application 62/698,702, filed on Jul. 16, 2018.
Prior Publication US 2024/0074136 A1, Feb. 29, 2024
Int. Cl. H10B 10/00 (2023.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC H10B 10/18 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A circuit layout comprising:
a first layout circuit comprising:
a first n-type transistor and a second n-type transistor disposed in a first p-type doped region; and
a first p-type transistor and a second p-type transistor disposed in a first n-type doped region,
wherein the first n-type doped region is disposed immediately adjacent to the first p-type doped region in a first direction;
a second layout circuit diagonally located with respect to the first layout circuit, the second layout circuit comprising:
third and fourth p-type transistors disposed in a second n-type doped region,
wherein the second n-type doped region is diagonally arranged with the first n-type doped region; and
third and fourth n-type transistors disposed in a second p-type doped region,
wherein the second p-type doped region is immediately adjacent to the second n-type doped region,
wherein the second n-type doped region is diagonal to the first n-type doped region, and
wherein there is no transitional space between the second n-type doped region and the first n-type doped region.