CPC H01L 27/124 (2013.01) [H10K 59/131 (2023.02)] | 15 Claims |
1. An array substrate, comprising: a display region comprising signal lines, a peripheral region comprising a bonding region, and signal line leads disposed in the peripheral region; wherein
the bonding region comprises at least two rows of signal line input terminals disposed on a first substrate, the signal line input terminals being electrically connected to the signal lines;
the signal line input terminal comprises an etched conductive layer, at least the etched conductive layers in two adjacent signal line input terminals disposed in a same row being disposed on different layers; and
one end of each of the signal line leads is electrically connected to the signal line and the other end of each of the signal line leads is electrically connected to the signal line input terminal; parts, proximal to the signal line input terminals, of two adjacent signal line leads are disposed on different layers; and an orthogonal projection of the signal line lead electrically connected to a first signal line input terminal onto the first substrate falls between orthogonal projections of the two adjacent signal line input terminals in an adjacent row of signal line input terminals onto the first substrate, wherein the first signal line input terminal being any one of one row of signal line input terminals and the adjacent rows of signal line input terminals being disposed between the first signal line input terminal and the display region.
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