US 12,170,283 B2
Capacitor cell and structure thereof
Chien-Yao Huang, Taipei (TW); Wun-Jie Lin, Hsinchu (TW); Chia-Wei Hsu, New Taipei (TW); and Yu-Ti Su, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 14, 2023, as Appl. No. 18/300,563.
Application 18/300,563 is a continuation of application No. 17/210,873, filed on Mar. 24, 2021, granted, now 11,664,381.
Application 17/210,873 is a continuation of application No. 16/591,064, filed on Oct. 2, 2019, granted, now 10,971,495, issued on Apr. 6, 2021.
Application 16/591,064 is a continuation of application No. 15/495,106, filed on Apr. 24, 2017, granted, now 10,475,793, issued on Nov. 12, 2019.
Prior Publication US 2023/0299088 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 27/02 (2006.01); H01L 27/08 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/861 (2006.01); H01L 29/94 (2006.01)
CPC H01L 27/0928 (2013.01) [H01L 27/0262 (2013.01); H01L 27/0266 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/94 (2013.01); H01L 27/0811 (2013.01); H01L 29/861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A capacitor cell, comprising:
a first PMOS transistor coupled between and directly connected to a power supply and a first node, having a gate directly connected to a second node;
a first NMOS transistor coupled between and directly connected to a ground and the second node, having a gate directly connected to the first node;
a second PMOS transistor coupled between and directly connected to the second node and the first node, having a gate directly connected to the second node;
a second NMOS transistor coupled between and directly connected to the first node and the ground, having a gate directly connected to the first node;
a first N+ doped region in an N-type well region and coupled to the power supply;
a first P+ doped region in a P-type well region and coupled to the ground;
a first isolation region between the first PMOS transistor and the first N+ doped region;
a second isolation region between the second NMOS transistor and the first P+ doped region; and
a third isolation region between the P-type well region and the N-type well region,
wherein sources of the first and second NMOS transistors share a second N+ doped region in the P-type well region, and the first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors,
wherein source of the first PMOS transistor is directly connected to the power supply, and sources of the first and second NMOS transistors are directly connected to the ground.