CPC H01L 27/1248 (2013.01) [H01L 27/1225 (2013.01)] | 20 Claims |
1. A display panel, comprising:
a base substrate;
a first transistor and a second transistor that are formed on the base substrate, wherein the first transistor comprises a first active layer, a first gate, a first source and a first drain, and the first active layer comprises silicon; and wherein the second transistor comprises a second active layer, a second gate, a second source and a second drain, the second active layer comprises an oxide semiconductor, and the second gate is located on a side of the second active layer facing away from the base substrate;
a first insulating layer, wherein the first insulating layer is located on a side of the second gate facing away from the base substrate, and the first insulating layer comprises an inorganic material; and
a planarization layer, wherein the planarization layer is located on a side of the first insulating layer facing away from the base substrate, and the planarization layer comprises an organic material,
wherein the first insulating layer comprises a first insulating sublayer and a second insulating sublayer, the second insulating sublayer is located on a side of the first insulating sublayer facing away from the base substrate, and a second compactness of the second insulating sublayer is greater than a first compactness of the first insulating sublayer; and
wherein the display panel further comprises a third insulating sublayer, wherein the third insulating sublayer is located on a side of the first insulating sublayer facing away from the base substrate.
|