US 12,170,260 B2
Semiconductor package and method of manufacturing the same
Yun Hwa Choi, Bucheon-si (KR)
Assigned to JMJ Korea Co., Ltd., Bucheon-si (KR)
Filed by JMJ Korea Co., Ltd., Bucheon-si (KR)
Filed on Dec. 6, 2021, as Appl. No. 17/543,617.
Claims priority of application No. 10-2021-0027532 (KR), filed on Mar. 2, 2021.
Prior Publication US 2022/0285304 A1, Sep. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/16 (2013.01) [H01L 23/49816 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 2224/10155 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81801 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a pad substrate on which a semiconductor chip is installed;
a solder formed on the pad substrate having a length same as or longer than a side of the semiconductor chip; and
an intagliated groove formed on the pad substrate having a length longer than at least the side of the semiconductor chip and filled with at least a certain amount of melted solder,
wherein the solder having a thickness of at least 1 μm or above is filled in the intagliated groove to have a length of at least 3 μm or above and an intermetallic compound layer is formed on a certain area included in an inner wall of the intagliated groove.