CPC G11C 16/30 (2013.01) | 20 Claims |
1. An apparatus comprising:
a set of memory components of a memory sub-system, the set of memory components comprising:
a first memory block comprising first units of linearly arranged memory cells;
a second memory block comprising second units of linearly arranged memory cells; and
a slit portion dividing the first and second memory blocks, the slit portion comprising a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells, holdup power being provided to the set of memory components from the capacitor in response to a power failure event associated with a regulator supply.
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