US 12,170,267 B2
Semiconductor device and method of manufacture
Jiun Yi Wu, Zhongli (TW); Chen-Hua Yu, Hsinchu (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 13, 2023, as Appl. No. 18/300,175.
Application 18/300,175 is a division of application No. 17/143,657, filed on Jan. 7, 2021, granted, now 11,664,350.
Claims priority of provisional application 63/027,609, filed on May 20, 2020.
Prior Publication US 2023/0253368 A1, Aug. 10, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/52 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/56 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 24/95 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
attaching interconnect structures to a carrier, wherein each one of the interconnect structures comprises conductive pillars, wherein the conductive pillars protrude from a top surface of the respective interconnect structure;
forming an encapsulant over the interconnect structures, wherein the encapsulant extends between adjacent ones of the interconnect structures;
performing a planarization process on the encapsulant to expose the conductive pillars, wherein after performing the planarization process the encapsulant and the conductive pillars have coplanar surfaces, wherein after performing the planarization process the encapsulant extends over the respective top surface of each interconnect structure;
forming first redistribution layers on the encapsulant and on the conductive pillars, wherein a bottom first redistribution layer of the first redistribution layers is electrically connected to the conductive pillars; and
bonding a semiconductor package to a top first redistribution layer of the first redistribution layers.