US 12,169,178 B2
IC fabrication flow with dynamic sampling for measurement
Jonas Hoehenberger, Kissing (DE); Moritz Steinberg, Freising (DE); Pietro Foglietti, Altdorf (DE); and Alexander Sirch, Freising (DE)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 29, 2022, as Appl. No. 17/955,706.
Claims priority of provisional application 63/341,502, filed on May 13, 2022.
Prior Publication US 2023/0366832 A1, Nov. 16, 2023
Int. Cl. G01N 21/95 (2006.01); G03F 7/00 (2006.01)
CPC G01N 21/9501 (2013.01) [G03F 7/705 (2013.01); G03F 7/70633 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit (IC), the method comprising:
processing a current plurality of semiconductor wafers in a fabrication flow having a sequence of process steps including a targeted process step, wherein the targeted process step adds to or subtracts from a material layer over the semiconductor wafers;
performing a metrological operation with respect to a measurement parameter associated with the material layer, the metrological operation performed responsive to a determination that the current plurality of semiconductor wafers is selected for measurement at the targeted process step, the determination based on a process capability index associated with the measurement parameter and a measurement history of a plurality of previous process runs at the targeted process step, each previous process run comprising a corresponding plurality of semiconductor wafers, and the process capability index is distributed between a first value corresponding to a first sampling rate for sampling a batch of process runs for measurement and a second value corresponding to a second sampling rate for sampling the batch of process runs for measurement;
on the condition that the metrological operation identifies at least one semiconductor wafer of the current plurality of semiconductor wafers as having an out-of-specification measurement, adjusting one or more processing conditions of the targeted process step; and
processing at least one subsequent semiconductor wafer containing the IC using the targeted process step after the adjusting.