CPC H03M 13/154 (2013.01) [H03M 13/1575 (2013.01); H03M 13/153 (2013.01); H03M 13/1545 (2013.01); H03M 13/373 (2013.01); H03M 13/3746 (2013.01)] | 10 Claims |
1. A memory system comprising:
an error correction code (ECC) decoder configured to receive data from a memory and comprising:
a syndrome generator configured to calculate at least one of syndrome vector and an erasure value;
an error-location polynomial generator configured to determine error location polynomials and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator;
an error value generator configured to confirm error values at one or more known error locations based upon the determined error/erasure value polynomials; and
an error location generator configured to conduct a search of error location combinations to find an error evaluation value to confirm error locations of specific errors based upon the error location polynomials;
wherein outputs of the error value generator and the error location generator are combined to produce corrected data, and
wherein the ECC decoder facilitates an iterative decoding operation by performing a single decoding attempt of a portion of a word received from a memory component of the memory and when failing to correct detected errors, iteratively performing decoding attempts on remaining portions of the word corresponds to remaining memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.
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