US 12,170,268 B2
Embedded metal lines
Stephen Morein, San Jose, CA (US)
Assigned to Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR TECHNOLOGIES LLC, San Jose, CA (US)
Filed on Mar. 22, 2024, as Appl. No. 18/614,310.
Application 18/614,310 is a continuation of application No. 18/145,375, filed on Dec. 22, 2022, granted, now 11,978,724.
Application 18/145,375 is a continuation of application No. 17/107,710, filed on Nov. 30, 2020, granted, now 11,621,246, issued on Apr. 4, 2023.
Application 17/107,710 is a continuation of application No. 16/369,631, filed on Mar. 29, 2019, granted, now 10,854,578, issued on Dec. 1, 2020.
Prior Publication US 2024/0266326 A1, Aug. 8, 2024
Int. Cl. H01L 21/76 (2006.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 29/08 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/02532 (2013.01); H01L 21/3212 (2013.01); H01L 21/76802 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 23/528 (2013.01); H01L 25/50 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A method comprising:
providing a substrate having a back side and a top side opposite the back side, the substrate comprising active devices coupled to buried lines extending parallel to a major surface of the substrate, the active devices closer to the top side than the back side of the substrate; and
exposing the buried lines from the back side of the substrate.