CPC G06F 21/602 (2013.01) [G06F 7/588 (2013.01); G06F 21/64 (2013.01); G06F 21/79 (2013.01); G11C 7/1009 (2013.01); G06F 21/107 (2023.08)] | 20 Claims |
1. A data processing device comprising:
a memory configured to store each data word of a plurality of data words in the form of at least two respective shares;
a logic circuit configured to receive the at least two shares of at least one of the data words and to process the at least two shares to generate at least two shares of a result data word;
a remasking circuit configured to receive the at least two shares of at least one of the data words and refresh the at least two shares; and
an output circuit configured to selectively store one of (a) the at least two shares of the result data word and (b) the refreshed at least two shares, depending on a control sequence specifying a sequence of real operations and dummy operations.
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