US 12,170,241 B2
Embedded metal insulator metal structure
Feng-Wei Kuo, Hsinchu (TW); and Wen-Shiang Liao, Miaoli (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 10, 2022, as Appl. No. 17/837,517.
Application 17/837,517 is a division of application No. 16/690,535, filed on Nov. 21, 2019, granted, now 11,362,026.
Claims priority of provisional application 62/877,638, filed on Jul. 23, 2019.
Prior Publication US 2022/0301994 A1, Sep. 22, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/49589 (2013.01) [H01L 21/02422 (2013.01); H01L 21/31055 (2013.01); H01L 21/76832 (2013.01); H01L 23/29 (2013.01); H01L 23/49827 (2013.01); H01L 23/5223 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02372 (2013.01); H01L 2924/19041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an interconnect structure on a substrate;
forming a through interposer via (TIV) structure on the interconnect structure;
attaching a die to the substrate and adjacent to the TIV structure;
forming a dielectric layer on a top surface of the TIV structure;
forming a metal layer on a top surface of the dielectric layer;
patterning the metal layer to form a side surface of the metal layer coplanar with a side surface of the TIV structure; and
forming a redistribution layer (RDL) on the die and the metal layer.