CPC H03F 3/45475 (2013.01) | 19 Claims |
1. A circuit for sampling and holding electrical signals comprising:
a sample and hold amplifier comprising:
a first input node;
a first output node;
at least two capacitors, where each capacitor of the at least two capacitors comprises a bottom plate and a top plate, where each respective top plate is coupled to the first input node and the first output node;
a first PMOS transistor comprising:
a gate node connected to a bottom plate of a first capacitor of the at least two capacitors; and
a drain node coupled to an input node of a first current mirror, where an output of the first current mirror is coupled to a second output node of the sample and hold amplifier; and
a first NMOS transistor comprising:
a gate node connected to a bottom plate of a second capacitor of the at least two capacitors; and
a drain node coupled to an input node of a second current mirror, where an output of the second current mirror is coupled to the second output node of the sample and hold amplifier.
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