CPC G06F 30/33 (2020.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0673 (2013.01); G06N 10/00 (2019.01)] | 20 Claims |
1. A method for increasing a rate of simulation for quantum computing devices, comprising:
receiving a device definition for a quantum computing device, wherein:
the quantum computing device includes a plurality of gates and a plurality of modes;
each gate of the plurality of gates is coupled to a respective set of one or more of the plurality of modes; and
the device definition includes a plurality of sets of gate values, wherein a respective set of gate values indicates modification by a respective gate of an input pattern probability;
receiving state information, which includes:
a plurality of input patterns, wherein each of the input patterns includes a respective plurality of input pattern values, and wherein each input pattern value of the plurality of input pattern values indicates a number of input bosons that correspond to a respective mode of the plurality of modes; and
a plurality of amplitudes, wherein each respective amplitude of the plurality of amplitudes indicates a probability associated with a respective input pattern of the plurality of input patterns;
generating a first group of input patterns for a first gate, wherein the first group of input patterns includes a subset of the plurality of input patterns that meet grouping criteria; and
performing a simulation of the quantum computing device and increasing the rate of simulation of the quantum computing device based on the first group of input patterns, including:
for each input pattern of the first group of input patterns:
generating a respective set of gate-input-pattern values by combining the respective input pattern with the first gate; and
for each output pattern of a set of output patterns derived from the first group of input patterns:
generating a respective set of gate-output-pattern values by applying the respective output pattern to the respective set of gate-input-pattern values; and
determining a representative output value that corresponds to the respective set of gate-output-pattern values.
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