CPC G06F 9/4401 (2013.01) [G06F 8/65 (2013.01); G06F 9/3802 (2013.01)] | 24 Claims |
1. A system comprising:
a memory programmed with multiple firmware images, wherein each firmware image of the multiple firmware images has an associated entry point that is distinct from the entry point of the other firmware images;
a processor that fetches instructions of the multiple firmware images from the memory and executes the fetched instructions;
a hardware register writable with an address; and
a controller that is external to the processor and that is configured to, with respect to each reset of a sequence of resets of the processor:
hold the processor in the reset;
read an entry point of one of the firmware images from the hardware register;
write the entry point to the processor; and
release the processor from the reset to cause the processor to fetch its first instruction out of the reset from the memory at the entry point read from the hardware register;
wherein the multiple firmware images comprise:
a boot firmware image;
a mission mode firmware image; and
at least one other firmware image.
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