US 12,170,735 B2
Chip device and method for a randomized logic encryption
Alexander Zeh, Munich (DE); Rolf Baltes, Munich (DE); and Andreas Salomon, Munich (DE)
Assigned to Hensoldt Sensors GmbH, Taufkirchen (DE)
Filed by Hensoldt Sensors GmBH, Taufkirchen (DE)
Filed on Feb. 18, 2022, as Appl. No. 17/675,480.
Claims priority of application No. 21158414 (EP), filed on Feb. 22, 2021.
Prior Publication US 2022/0271953 A1, Aug. 25, 2022
Int. Cl. H04L 9/32 (2006.01); B33Y 80/00 (2015.01); H04L 9/08 (2006.01); B28B 1/00 (2006.01); B33Y 10/00 (2015.01)
CPC H04L 9/3278 (2013.01) [B33Y 80/00 (2014.12); H04L 9/0894 (2013.01); B28B 1/001 (2013.01); B33Y 10/00 (2014.12); H04L 2209/08 (2013.01); H04L 2209/12 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A chip device, comprising:
a logic circuitry protected by a randomized logic encryption based on a key for preventing a designated usage of the logic circuitry by an unauthorized user;
a physically unclonable function, PUF, being configured to generate a device-specific response based on a challenge;
a storage having stored the challenge and a data element, the data element being an encryption of the key with the response of the PUF as an encryption key; and
a chip enabler with one or more registers, the enabler being configured to enable the logic circuitry for the designated usage only, when the key is transferred to the register(s), the key being a decryption of the data element with the response as the encryption key,
wherein the logic circuitry comprises regular gates and a plurality of logic key gates defining the logic encryption, wherein the logic encryption is defined in that the designated usage is enabled only if bits of the key in the register(s) are correctly received by the logic key gates, which are connected to the register(s).