CPC H01L 29/7856 (2013.01) [H01L 21/76229 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/66439 (2013.01); H01L 29/6681 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); B82Y 10/00 (2013.01)] | 20 Claims |
1. A device comprising:
a first stack of first semiconductor layers disposed on a substrate, wherein a topmost first semiconductor layer from the first stack of first semiconductor layers includes a first sidewall and an opposing second sidewall;
a first gate structure disposed on and interleaved with the first stack of first semiconductor layers, wherein the first gate structure includes a first gate electrode and a first gate dielectric layer;
a first isolation structure disposed adjacent to the first sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers, wherein the first gate dielectric layer and the first gate electrode fill space between the first isolation structure and the first sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers;
a second isolation structure disposed adjacent to and physically contacting the second sidewall of the topmost first semiconductor layer from the first stack of first semiconductor layers; and
a dielectric isolation structure disposed on the substrate, wherein the first isolation structure interfaces with a first portion of the dielectric isolation structure and the second isolation structure interfaces with a second portion of the dielectric isolation structure.
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