US 12,169,419 B2
Clock generating circuit and method for trimming period of oscillator clock signal
Hyunil Kim, Seongnam-si (KR); Jisu Kang, Seoul (KR); Taewook Park, Seoul (KR); and Hongmook Choi, Bucheon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 15, 2022, as Appl. No. 17/841,078.
Claims priority of application No. 10-2021-0078994 (KR), filed on Jun. 17, 2021.
Prior Publication US 2022/0404859 A1, Dec. 22, 2022
Int. Cl. G06F 1/10 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G11C 29/02 (2006.01); G11C 29/56 (2006.01); H03K 21/38 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G11C 29/023 (2013.01); G11C 29/56004 (2013.01); H03K 21/38 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A clock generating circuit comprising:
an oscillator configured to output an oscillator clock signal having a period based on a trim value;
a clock counter configured to count the oscillator clock signal for a reference time;
a finite state machine configured to obtain, from the clock counter, a count value of the oscillator clock signal that is counted, and in a test mode, compare the count value with a target count value and change the trim value based on a comparison result and determine a final trim value based on the trim value that is changed; and
a non-volatile memory that stores the final trim value that is determined,
wherein the oscillator is configured to output the oscillator clock signal having a shorter period as the trim value decreases.