US 12,170,523 B2
Current-to-digital converter
Tantan Zhang, Singapore (SG); and Yuan Gao, Singapore (SG)
Assigned to AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, Singapore (SG)
Appl. No. 17/997,967
Filed by Agency for Science, Technology and Research, Singapore (SG)
PCT Filed Apr. 27, 2021, PCT No. PCT/SG2021/050232
§ 371(c)(1), (2) Date Dec. 2, 2022,
PCT Pub. No. WO2021/225518, PCT Pub. Date Nov. 11, 2021.
Claims priority of application No. 10202004084S (SG), filed on May 4, 2020.
Prior Publication US 2023/0179221 A1, Jun. 8, 2023
Int. Cl. H03M 1/46 (2006.01); H03M 3/00 (2006.01); H03M 1/66 (2006.01)
CPC H03M 1/46 (2013.01) [H03M 3/426 (2013.01); H03M 3/458 (2013.01); H03M 1/662 (2013.01); H03M 3/50 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A current-to-digital converter module comprising:
a modulation switch, SWK, configured to modulate an input current, IIN, to produce a scaled current, IINK, wherein the switch SWK is controlled by a modulation clock FK;
a delta-sigma analogue-to-digital converter, ΔΣ ADC, comprising an integrator coupled to a hysteresis comparator that is coupled to a D-type Flip-Flop being driven by a master clock, Fs, whereby an inverting output from the D-type Flip-Flop is coupled to an inverting input of the integrator using a 1-bit feedback current digital-to-analogue converter, DAC, the ΔΣ ADC being configured to generate digital outputs at a non-inverting output and the inverting output of the D-type Flip-Flop based on a balanced current, IBAL, received at the inverting input of the integrator, whereby the balanced current IBAL comprises a summation of the scaled current IINK with a reference current, IREF, produced by the 1-bit feedback current DAC;
a successive-approximation-register (SAR) control logic configured to generate control signals based on the non-inverting outputs from the D-type Flip-Flop, a reset clock signal and the master clock Fs; and
a clock generator module that is driven by the master clock, Fs, being configured to use the control signals from the SAR control logic to determine an optimal modulation clock FK for controlling the switch SWK.