US 12,170,265 B2
Semiconductor package
Chao-I Wu, Hsinchu County (TW); Yu-Ming Lin, Hsinchu (TW); and Sai-Hooi Yeong, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 2, 2020, as Appl. No. 17/086,479.
Claims priority of provisional application 63/045,202, filed on Jun. 29, 2020.
Prior Publication US 2021/0407966 A1, Dec. 30, 2021
Int. Cl. H01L 25/065 (2023.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 27/06 (2006.01); H01L 27/22 (2006.01); H10B 61/00 (2023.01)
CPC H01L 25/0657 (2013.01) [G11C 5/04 (2013.01); G11C 5/06 (2013.01); H01L 23/5384 (2013.01); H01L 24/14 (2013.01); H01L 27/0688 (2013.01); H10B 61/00 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a processor die comprising a memory cache;
a storage module comprising a cache die and a memory die stacked over one another, and electrically connected to the processor die, wherein the cache die is configured to hold copies of data stored in the memory die and frequently used by the processor die, wherein cache density of the cache die is greater than cache density of the memory cache of the processor die; and
a package substrate on which the processor die and the storage module are disposed.