US 12,169,142 B2
Integrated circuit with sequentially-coupled charge storage and associated techniques
Eric A. G. Webster, Santa Clara, CA (US); Todd Rearick, Cheshire, CT (US); and Thomas Raymond Thurston, Guilford, CT (US)
Assigned to Quantum-Si Incorporated, Branford, CT (US)
Filed by Quantum-Si Incorporated, Branford, CT (US)
Filed on Oct. 18, 2023, as Appl. No. 18/489,841.
Application 18/489,841 is a division of application No. 17/507,585, filed on Oct. 21, 2021.
Claims priority of provisional application 63/104,393, filed on Oct. 22, 2020.
Prior Publication US 2024/0044703 A1, Feb. 8, 2024
Int. Cl. G01J 1/44 (2006.01); B01J 19/00 (2006.01); H01L 27/146 (2006.01); H01L 27/148 (2006.01)
CPC G01J 1/44 (2013.01) [B01J 19/0046 (2013.01); H01L 27/14683 (2013.01); H01L 27/14818 (2013.01); H01L 27/14825 (2013.01); B01J 2219/00504 (2013.01); B01J 2219/00576 (2013.01); B01J 2219/00587 (2013.01); B01J 2219/00689 (2013.01); B01J 2219/00698 (2013.01); G01J 2001/446 (2013.01)] 20 Claims
OG exemplary drawing
 
8. An integrated circuit, comprising:
a photodetection region configured to generate charge carriers in response to receiving incident photons;
a first charge storage region electrically coupled to the photodetection region to receive charge carriers; and
a second charge storage region electrically coupled to the first charge storage region to receive charge carriers,
wherein the integrated circuit is configured to read out charge carriers from the second charge storage region while the first charge storage region receives charge carriers from the photodetection region.