CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] | 18 Claims |
1. A memory device, comprising:
a semiconductor layer extending in a lateral plane;
a peripheral circuit comprising a peripheral transistor in contact with the semiconductor layer;
an array of memory cells disposed on a lateral side of the semiconductor layer and the peripheral circuit, wherein each of the memory cells comprises a vertical transistor extending in a first direction perpendicular to the lateral plane, and a storage unit coupled to the vertical transistor, the vertical transistor comprises a semiconductor body extending in the first direction, and a gate structure in contact with one or more lateral sides of the semiconductor body, and the semiconductor body is aligned with the semiconductor layer in the lateral plane; and
bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction.
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