US 12,170,071 B2
Software Vsync filtering
Nan Zhang, Beijing (CN); Long Han, Shanghai (CN); and Yongjun Xu, Beijing (CN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 26, 2024, as Appl. No. 18/424,699.
Application 18/424,699 is a continuation of application No. 17/758,286, granted, now 11,935,502, previously published as PCT/CN2020/141179, filed on Dec. 30, 2020.
Claims priority of application No. PCT/CN2019/130447 (WO), filed on Dec. 31, 2019.
Prior Publication US 2024/0242690 A1, Jul. 18, 2024
Int. Cl. G09G 3/36 (2006.01); G09G 5/00 (2006.01); G09G 5/18 (2006.01)
CPC G09G 5/005 (2013.01) [G09G 5/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of display processing, comprising:
receiving a hardware Vsync signal from a display using a video mode;
generating a hardware timestamp signal based on the hardware Vsync signal;
determining a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames;
determining whether the delay for the pulse is over a threshold; and
controlling rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold.