CPC G11C 16/10 (2013.01) [G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 16/0483 (2013.01)] | 18 Claims |
1. An operating method of a non-volatile memory device, the operating method comprising:
simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines;
sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and
sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.
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