US 12,170,317 B2
Semiconductor device, and method of manufacturing the semiconductor device
Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 14, 2022, as Appl. No. 17/575,707.
Application 17/575,707 is a continuation of application No. 16/618,831, granted, now 11,227,920, previously published as PCT/IB2018/053629, filed on May 23, 2018.
Claims priority of application No. 2017-111144 (JP), filed on Jun. 5, 2017.
Prior Publication US 2022/0140090 A1, May 5, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 29/24 (2006.01)
CPC H01L 29/24 (2013.01) [H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a memory cell array, the memory cell array comprising:
a first conductor over a base;
a first transistor over the first conductor, the first transistor comprising:
a second conductor comprising a first opening;
a first part of an insulator provided in contact with an inner side of the first opening; and
a first part of an oxide provided in contact with an inner side of the first part of the insulator; and
a second transistor stacked over the first transistor, the second transistor comprising:
a third conductor comprising a second opening;
a second part of the insulator provided in contact with an inner side of the second opening; and
a second part of the oxide provided in contact with an inner side of the second part of the insulator,
wherein the oxide comprises In, an element M, and Zn,
wherein the element M is at least one of Al, Ga, Y, and Sn, and
wherein the first part of the insulator is thicker than the second part of the insulator.