US 12,170,118 B2
Memory system
Yoshihisa Kojima, Kawasaki Kanagawa (JP); Shunichi Igahara, Fujisawa Kanagawa (JP); and Toshikatsu Hida, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 23, 2022, as Appl. No. 18/088,129.
Claims priority of application No. 2022-079428 (JP), filed on May 13, 2022.
Prior Publication US 2023/0367487 A1, Nov. 16, 2023
Int. Cl. G11C 8/00 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3404 (2013.01) [G11C 16/16 (2013.01); G11C 8/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a non-volatile memory including a first block including a plurality of memory cells, the first block including a first sub-block and a second sub-block, the first sub-block including a first memory cell, the second sub-block including a second memory cell, the second memory cell being coupled in series to the first memory cell or coupled in parallel to the first memory cell with respect to a single bit line; and
a memory controller configured to instruct the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory, wherein
the memory controller is further configured to:
in response to a first value corresponding to the first sub-block having reached a first threshold value,
read first data from the first sub-block;
execute an error correction process on the first data read from the first sub-block; and
write the first data on which the error correction process has been executed into the non-volatile memory.