US 12,170,266 B2
Semiconductor package
Wanho Park, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 29, 2023, as Appl. No. 18/216,445.
Application 18/216,445 is a continuation of application No. 17/216,142, filed on Mar. 29, 2021, granted, now 11,721,671.
Claims priority of application No. 10-2020-0089078 (KR), filed on Jul. 17, 2020.
Prior Publication US 2023/0343752 A1, Oct. 26, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/16 (2013.01); H01L 23/31 (2013.01); H01L 23/5386 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a chip stack comprising semiconductor chips vertically stacked on a substrate;
pillars between the substrate and the chip stack;
an adhesive layer on a bottom surface of a lowermost semiconductor chip of the semiconductor chips;
a first lower protective layer between the adhesive layer and the pillars;
and a mold layer covering the chip stack,
wherein the first lower protective layer includes a recess recessed from a bottom surface of the first lower protective layer toward a top surface of the first lower protective layer, and
wherein the mold layer fills a space between the pillars and filling the recess.
 
10. A semiconductor package comprising:
a chip stack comprising semiconductor chips vertically stacked on a substrate;
wherein the chip stack comprises a first semiconductor chip located at a lowest level and a second semiconductor chip located at a highest level of the semiconductor chips;
upper conductive pads on a top surface of the substrate;
pillars between the top surface of the substrate and the chip stack, wherein at least one of the pillars comprises a lower semiconductor chip;
wherein the lower semiconductor chip includes lower chip pads on a lower surface of the lower semiconductor chip;
a lower connection terminal interposed between the upper conductive pads and the lower chip pads;
an adhesive layer on a bottom surface of the first semiconductor chip;
a first lower protective layer between the adhesive layer and the pillars; and
a mold layer covering the chip stack and filling a space between the pillars.