CPC G11C 7/109 (2013.01) [G11C 7/1084 (2013.01); G11C 7/222 (2013.01); G11C 5/04 (2013.01); G11C 7/1057 (2013.01); G11C 2207/101 (2013.01)] | 24 Claims |
1. An apparatus, comprising:
a buffer comprising a first interface and a second interface, the first interface configured to be coupled with a host device and the second interface configured to be coupled with one or more memory dies, the buffer configured to:
receive, at the first interface and from the host device, data communicated at a first frequency and according to a first signaling scheme comprising a first quantity of voltage levels; and
output, from the second interface to a memory die of the one or more memory dies, the data at a second frequency lower than the first frequency and according to a second signaling scheme comprising a second quantity of voltage levels, wherein the second quantity of voltage levels is greater than the first quantity of voltage levels.
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