US 12,170,291 B2
Display device
Hisao Ikeda, Zama (JP); Kouhei Toyotaka, Atsugi (JP); Hideaki Shishido, Atsugi (JP); Hiroyuki Miyake, Atsugi (JP); Kohei Yokoyama, Fujisawa (JP); Yasuhiro Jinbo, Isehara (JP); Yoshitaka Dozen, Atsugi (JP); Takaaki Nagata, Isehara (JP); and Shinichi Hirasa, Isehara (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 11, 2023, as Appl. No. 18/534,908.
Application 18/534,908 is a continuation of application No. 17/991,893, filed on Nov. 22, 2022, granted, now 11,881,489.
Application 17/991,893 is a continuation of application No. 16/793,543, filed on Feb. 18, 2020, granted, now 11,552,107, issued on Jan. 10, 2023.
Application 16/793,543 is a continuation of application No. 15/366,255, filed on Dec. 1, 2016, granted, now 10,573,667, issued on Feb. 25, 2020.
Claims priority of application No. 2015-241714 (JP), filed on Dec. 11, 2015; and application No. 2016-050692 (JP), filed on Mar. 15, 2016.
Prior Publication US 2024/0105737 A1, Mar. 28, 2024
Int. Cl. H01L 27/12 (2006.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); H01L 29/786 (2006.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01); G09G 3/36 (2006.01); G09G 5/391 (2006.01)
CPC H01L 27/124 (2013.01) [G09G 3/2003 (2013.01); G09G 3/3233 (2013.01); H01L 27/1225 (2013.01); H01L 27/1266 (2013.01); H01L 29/78648 (2013.01); H10K 59/131 (2023.02); H10K 59/352 (2023.02); H10K 59/353 (2023.02); G09G 3/3648 (2013.01); G09G 5/391 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0443 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0842 (2013.01); G09G 2320/0295 (2013.01); G09G 2320/043 (2013.01); G09G 2320/0693 (2013.01)] 4 Claims
OG exemplary drawing
 
1. An EL display device, comprising:
a first EL display element;
a second EL display element;
a first pixel circuit;
a second pixel circuit;
a first gate line;
a second gate line;
a first wiring;
a second wiring; and
a third wiring,
wherein the first EL display element comprises a first pixel electrode,
wherein the second EL display element comprises a second pixel electrode,
wherein the first EL display element is configured to emit one of a red color and a green color, and the second EL display element is configured to emit the other of the red color and the green color,
wherein the first pixel circuit is adjacent to the second pixel circuit,
wherein the first pixel circuit comprises a first transistor, a second transistor, and a first capacitor,
wherein the second pixel circuit comprises a third transistor, a fourth transistor, and a second capacitor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the gate of the first transistor is electrically connected to one electrode of the first capacitor,
wherein the other electrode of the first capacitor is electrically connected to the first wiring,
wherein a gate of the second transistor is controlled by the first gate line,
wherein when the first transistor is turned on so that the first wiring is electrically connected to the first pixel electrode through one of a source and a drain of the first transistor, a channel formation region of the first transistor, and the other of the source and the drain of the first transistor, a first current flows between the first wiring and the first pixel electrode through the one of the source and the drain of the first transistor, the channel formation region of the first transistor, and the other of the source and the drain of the first transistor,
wherein when the second transistor is in an on state, a potential of the second wiring is supplied to the gate of the first transistor through the other of the source and the drain of the second transistor, a channel formation region of the second transistor, and the one of the source and the drain of the second transistor,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the gate of the third transistor is electrically connected to one electrode of the second capacitor,
wherein the other electrode of the second capacitor is electrically connected to the first wiring,
wherein a gate of the fourth transistor is controlled by the second gate line,
wherein when the third transistor is turned on so that the first wiring is electrically connected to the second pixel electrode through one of a source and a drain of the third transistor, a channel formation region of the third transistor, and the other of the source and the drain of the third transistor, a second current flows between the first wiring and the second pixel electrode through the one of the source and the drain of the third transistor, the channel formation region of the third transistor, and the other of the source and the drain of the third transistor,
wherein when the fourth transistor is in an on state, a potential of the third wiring is supplied to the gate of the third transistor through the other of the source and the drain of the fourth transistor, a channel formation region of the fourth transistor, and the one of the source and the drain of the fourth transistor,
wherein the first pixel electrode comprises a region overlapping with the channel formation region of the first transistor,
wherein the first pixel electrode does not overlap with the channel formation region of the fourth transistor,
wherein the first pixel electrode does not overlap with the channel formation region of the second transistor,
wherein the second pixel electrode comprises a region overlapping with the channel formation region of the third transistor,
wherein the second pixel electrode does not overlap with the channel formation region of the fourth transistor,
wherein the second pixel electrode does not overlap with the channel formation region of the first transistor, and
wherein the second pixel electrode comprises a region overlapping with the channel formation region of the second transistor.