US 12,169,466 B2
Distributed arbitration for shared data path
Thomas Lorne Drabenstott, Cary, NC (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 26, 2023, as Appl. No. 18/160,127.
Claims priority of provisional application 63/422,407, filed on Nov. 3, 2022.
Prior Publication US 2024/0152477 A1, May 9, 2024
Int. Cl. G06F 13/42 (2006.01); G06F 9/52 (2006.01)
CPC G06F 13/42 (2013.01) [G06F 9/52 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a data pipeline connecting multiple data sources to a data receiver; and
a plurality of data arbiters each configured to merge data from a respective data source of the multiple data sources to the data pipeline at a distinct point in the pipeline, each of the plurality of data arbiters including:
a multiplexer configured to selectively pass, to the data pipeline, an upstream data packet or a local data packet from the respective data source;
a register configured to store an indication of data packets passed by the multiplexer based on the respective data source originating the data packet; and
a controller configured to control the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.