US 12,169,701 B2
Multiplier circuit
Shunpei Yamazaki, Setagaya (JP); Hajime Kimura, Atsugi (JP); and Takahiro Fukutome, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 6, 2023, as Appl. No. 18/242,603.
Application 18/242,603 is a continuation of application No. 17/673,932, filed on Feb. 17, 2022, granted, now 11,755,285.
Application 17/673,932 is a continuation of application No. 16/649,948, granted, now 11,262,981, issued on Mar. 1, 2022, previously published as PCT/IB2018/058647, filed on Nov. 5, 2018.
Claims priority of application No. 2017-221455 (JP), filed on Nov. 17, 2017; and application No. 2018-027238 (JP), filed on Feb. 19, 2018.
Prior Publication US 2024/0053961 A1, Feb. 15, 2024
Int. Cl. G06G 7/16 (2006.01); G06F 7/499 (2006.01); G06F 7/501 (2006.01); G06F 7/57 (2006.01); G06F 9/30 (2018.01)
CPC G06F 7/49942 (2013.01) [G06F 7/4991 (2013.01); G06F 7/501 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06G 7/16 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A multiplier circuit comprising:
a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor; and
a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor,
wherein a gate of the first transistor is electrically connected to one electrode of the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the other electrode of the first capacitor,
wherein a gate of the second transistor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,
wherein a gate of the third transistor is electrically connected to one electrode of the third capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the other electrode of the third capacitor,
wherein a gate of the fourth transistor is electrically connected to one electrode of the fourth capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the one electrode of the fourth capacitor, and
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.