US 12,169,719 B1
Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine
Avinash Sodani, San Jose, CA (US); Ulf Hanebutte, Gig Harbor, WA (US); Senad Durakovic, Palo Alto, CA (US); Hamid Reza Ghasemi, Sunnyvale, CA (US); and Chia-Hsin Chen, Santa Clara, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Jan. 6, 2021, as Appl. No. 17/248,045.
Application 17/248,045 is a continuation of application No. 16/226,508, filed on Dec. 19, 2018, granted, now 11,086,633.
Claims priority of provisional application 62/675,076, filed on May 22, 2018.
Claims priority of provisional application 62/644,352, filed on Mar. 16, 2018.
Claims priority of provisional application 62/628,130, filed on Feb. 8, 2018.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 15/78 (2006.01); G06F 17/16 (2006.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01); G06F 9/30 (2018.01); G06F 15/80 (2006.01); G06N 5/04 (2023.01); G06N 20/20 (2019.01)
CPC G06F 9/3877 (2013.01) [G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 15/7807 (2013.01); G06F 17/16 (2013.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01); G06F 9/3001 (2013.01); G06F 15/7864 (2013.01); G06F 15/8023 (2013.01); G06F 2212/602 (2013.01); G06N 5/04 (2013.01); G06N 20/20 (2019.01)] 42 Claims
OG exemplary drawing
 
19. A method comprising:
receiving a set of commands for performance-critical operations in a first instruction set architecture (ISA) format from a core;
generating a second ISA format from the first ISA format;
streaming the set of commands in the second ISA format to an inference engine, wherein the set of commands in the first ISA format is an asynchronous instruction set; and
executing by the inference engine the stream of the set of commands in the second ISA format to program a plurality of components within the inference engine to perform an ML operation.