US 12,171,106 B2
Non-volatile memory with dual gated control
Katherine H. Chiang, New Taipei (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/883,691.
Application 17/883,691 is a division of application No. 17/116,024, filed on Dec. 9, 2020, granted, now 11,716,862.
Claims priority of provisional application 63/031,035, filed on May 28, 2020.
Prior Publication US 2022/0384444 A1, Dec. 1, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 29/786 (2006.01); H10B 99/00 (2023.01)
CPC H10B 99/00 (2023.02) [H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming multiple memory stacks stacked over one another and stacked over a semiconductor substrate;
performing an etch to pattern the memory stacks into multiple columns of memory stack structures, wherein read bitline (RBL) trenches and write wordline (WWL) trenches are on opposite sides of the multiple columns of memory stack structures to separate the multiple columns of memory stack structures from one another;
performing a first lateral etch to remove outermost conductive regions from each memory stack structure, thereby forming first recesses in sidewalls of each memory stack structure; and
filling the RBL trenches, the WWL trenches, and the first recesses with a dielectric material; and
re-opening the RBL trenches while leaving the WWL trenches filled with the dielectric material.