US 12,170,246 B2
Semiconductor device with contact structure
Chung-Liang Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,739.
Application 18/362,739 is a division of application No. 17/193,807, filed on Mar. 5, 2021, granted, now 11,776,900.
Claims priority of provisional application 63/042,172, filed on Jun. 22, 2020.
Prior Publication US 2023/0378057 A1, Nov. 23, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/486 (2013.01); H01L 21/76802 (2013.01); H01L 21/76841 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first dielectric layer;
a transistor including a source/drain terminal having a top surface substantially coplanar with a top surface of the first dielectric layer;
a second dielectric layer on the first dielectric layer;
a first trench in the second dielectric layer exposing the source/drain terminal and defining a sidewall of the second dielectric layer;
a silicide layer in contact with the top surface of the source/drain terminal in the trench;
a metal layer on the silicide in the trench and including a substantially planar bottom surface in contact with a top surface of the silicide layer and a substantially planar top surface;
a first barrier layer having a planar bottom surface in contact with the top surface of the metal layer in the trench and substantially planar top surface;
a second barrier layer having a planar bottom surface in contact with the top surface of the first barrier layer, the second barrier layer in contact with the sidewall of the second dielectric layer and having a vertical extent in the trench higher than a vertical extent of the first barrier layer in the trench; and
a conductive plug positioned in the trench and in contact with the second barrier layer.