US 12,169,671 B2
Apparatus and method for mapping foundational components during design porting from one process technology to another process technology
Chih-Yuan Stephen Yu, San Jose, CA (US); Boh-Yi Huang, San Jose, CA (US); Chao-Chun Lo, San Jose, CA (US); and Xiang Guo, San Jose, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/231,762.
Application 18/231,762 is a continuation of application No. 17/865,084, filed on Jul. 14, 2022, granted, now 11,783,104.
Application 17/865,084 is a continuation of application No. 17/239,000, filed on Apr. 23, 2021, granted, now 11,403,448.
Prior Publication US 2024/0037302 A1, Feb. 1, 2024
Int. Cl. G06F 30/30 (2020.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 115/06 (2020.01)
CPC G06F 30/323 (2020.01) [G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 2115/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for migrating a circuit design from a first semiconductor fabrication process to a second semiconductor fabrication process comprising:
receiving the circuit design;
parsing the circuit design into one or more standard cells forming an integrated circuit design;
forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells to equivalent target standard cells implemented in the second semiconductor fabrication process;
mapping the parsed one or more standard cells to the equivalent target standard cells using the plurality of mapping tables;
generating a file describing the circuit design in terms of the equivalent target standard cells; and
outputting migrated physical layout of the circuit design for manufacturing under the second semiconductor fabrication process.