US 12,170,119 B2
Memory device for performing program operation and method of operating the same
Jae Yeop Jung, Gyeonggi-do (KR); Dong Hun Kwak, Gyeonggi-do (KR); and Hyung Jin Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 1, 2022, as Appl. No. 17/829,876.
Claims priority of application No. 10-2021-0091838 (KR), filed on Jul. 13, 2021; and application No. 10-2021-0190111 (KR), filed on Dec. 28, 2021.
Prior Publication US 2023/0015493 A1, Jan. 19, 2023
Int. Cl. G11C 16/00 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A method of operating a memory device including a plurality of memory cell strings each including a plurality of memory cells coupled between a common source line and a bit line, a source select transistor coupled to a source select line between the common source line and the plurality of memory cells, a drain select transistor coupled to a drain select line between the bit line and the plurality of memory cells, and a plurality of dummy memory cells coupled between the plurality of memory cells and the source select transistor, the method comprising:
applying a first precharge voltage to the common source line in a first program loop among a plurality of program loops;
applying a first dummy voltage to at least one of a plurality of dummy word lines respectively coupled to the plurality of dummy memory cells in the first program loop;
applying a second precharge voltage higher than the first precharge voltage to the common source line in a second program loop after the first program loop among the plurality of program loops; and
applying a second dummy voltage higher than the first dummy voltage to the at least one dummy word line in the second program loop.