CPC H04N 25/77 (2023.01) [H04N 25/63 (2023.01); H04N 25/75 (2023.01)] | 18 Claims |
1. A pixel circuit, comprising:
an optically sensitive material (OSM) layer, configured to receive light to generate signal charges to be integrated into a node;
a P-well substrate;
a reset transistor, arranged within the P-well substrate, and having a source configured as the node;
an N-well region, arranged within the P-well substrate;
a readout transistor, arranged within the N-well region, and having a gate connected to the node; and
a row selection transistor, arranged within the N-well region, and coupled between the readout transistor and a readout line,
wherein the readout transistor and the row selection transistor are electrically separated from the P-well substrate by the N-well region, and
a drain of the reset transistor is configured to receive a reset voltage, which is arranged between +1 volt and −0.5 volt relative to a voltage of the P-well substrate to cause the readout transistor to operate within a linear region thereof.
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