CPC H01L 23/49816 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/5389 (2013.01); H01L 24/09 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/9222 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01)] | 20 Claims |
1. A method of manufacturing a semiconductor device, the method comprising:
planarizing a first surface, the first surface comprising a first external contact of a first die, a molding compound, a via located within a via die, and a second die, wherein the via extends from a first side of the via die to a second side of the via die, wherein the via has a straight sidewall as it extends from the first side to the second side; and
forming a redistribution layer over the first surface.
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