CPC H10B 63/845 (2023.02) [H10B 63/30 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02); G11C 13/0004 (2013.01); G11C 13/0028 (2013.01); G11C 2213/71 (2013.01); G11C 2213/79 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a plurality of contacts associated with a plurality of digit lines and extending through a substrate;
a first plurality of word line plates separated from a second plurality of word line plates by a trench;
a pair of pillars comprising at least one pillar that is configured as a digit line of the plurality of digit lines, each pillar of the pair of pillars configured to interact with the first plurality of word line plates and the second plurality of word line plates, and each pillar of the pair of pillars extending between, and in contact with, two insulating substrates;
a dielectric material positioned between a first pillar of the pair of pillars and a second pillar of the pair of pillars; and
a plurality of storage elements comprising chalcogenide material and in contact with the dielectric material, a word line plate of the first plurality or the second plurality of word line plates, and a pillar of the pair of pillars.
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