CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/061 (2013.01)] | 16 Claims |
1. A pixel driving circuit, comprising:
a driving circuit connected to a first node, a second node and a third node and configured to provide a driving current to the third node through the second node according to a signal from the first node;
a control circuit connected to a first enable signal terminal, the second node, a first power supply terminal and a fourth node and configured to create conduction between the second node and the fourth node in response to a signal from the first enable signal terminal, and create conduction between the first power supply terminal and the fourth node in response to the signal from the first enable signal terminal;
a voltage stabilization circuit connected to the fourth node, a second enable signal terminal and a reference voltage terminal and configured to transmit a signal from the reference voltage terminal to the fourth node in response to a signal from the second enable signal terminal; and
a first storage circuit connected between the first node and the fourth node and configured to store electric charges of the first node and the fourth node;
a first reset circuit connected to an initialization signal terminal and a fifth node, and configured to transmit a signal from the initialization signal terminal to the fifth node in response to at least one control signal; and
a second reset circuit connected to the first node and a further initialization signal terminal, and configured to transmit a signal from the further initialization signal terminal to the first node in response to at least one control signal;
wherein the second reset circuit is further connected to a reset signal terminal, a first gate driving signal terminal and a sixth node, and configured to create conduction between the further initialization signal terminal and the sixth node in response to a signal from the reset signal terminal and configured to create conduction between the sixth node and the first node in response to the signal from the first gate driving signal terminal.
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