US 12,171,094 B2
Semiconductor structure, formation method thereof and memory
Wei Wan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 27, 2021, as Appl. No. 17/486,696.
Application 17/486,696 is a continuation of application No. PCT/CN2021/106500, filed on Jul. 15, 2021.
Claims priority of application No. 202110750964.8 (CN), filed on Jul. 2, 2021.
Prior Publication US 2023/0005929 A1, Jan. 5, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/34 (2023.02) [H10B 12/053 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a channel located in the substrate, the channel being configured to form a gate structure; and
a convex portion arranged on an inner wall of the channel;
wherein the convex portion comprises a first convex portion arranged on a bottom wall of the channel, and shallow trenches are formed between the first convex portion and two sidewalls of the channel respectively.