CPC G11C 5/063 (2013.01) [G11C 5/025 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H10B 12/50 (2023.02); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/0002 (2013.01)] | 20 Claims |
1. A memory device comprising:
a first integrated circuit (IC) memory chip including
first memory core circuitry,
a first interface circuit decoupled from the first memory core circuitry, and
a first transfer circuit to transfer first data between a first number of core data paths of the first memory core circuitry and a second number of data paths coupled to at least one through-silicon-via (TSV), the second number of data paths being less than the first number of core data paths;
a second IC memory chip vertically stacked with the first IC memory chip, the second IC memory chip including
second memory core circuitry,
a second interface circuit coupled to the second memory core circuitry for transferring second data with a memory controller, the second interface circuit coupled to the at least one TSV for transferring the first data between the multiple core data paths of the first memory core circuitry and the memory controller.
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