CPC H04L 45/121 (2013.01) [H04L 45/22 (2013.01); H04L 45/24 (2013.01); H04L 45/28 (2013.01); H04L 47/30 (2013.01)] | 4 Claims |
1. A transmission apparatus that performs communication with a transmission side transmission apparatus via a transmission path of an active system and a transmission path of a standby system, the transmission apparatus comprising:
a plurality of first memories configured to store a signal of the transmission path of an active system and a signal of the transmission path of a standby system, respectively,
a second memory configured to have a capacity that is as large as allowable delay caused due to a maximum path difference between the transmission path of the active system and the transmission path of the standby system;
a memory connection controller configured to switch connection so that the second memory is connected to one of the plurality of first memories and causes a signal of the transmission path of the active system or the transmission path of the standby system to accumulate in the second memory, and
a path selector configured to select a path of a signal acquisition source between the transmission path of the active system and the transmission path of the standby system,
wherein the memory connection controller disconnects the connection of the second memory while waiting for communication in one transmission path between the transmission path of the active system and the transmission path of the standby system and reconnects the second memory to accumulate a signal of the transmission path of the active system or the transmission path of the standby system in which delay is less after the communication is recovered, and wherein the path selector switches the path of the signal acquisition source to the selected path after the second memory is connected,
wherein each of the memory connection controller and the path selector is implemented by:
i) computer executable instructions executed by at least one processor,
ii) at least one circuitry or
iii) a combination of computer executable instructions executed by at least one processor and at least one circuitry.
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