US 12,170,123 B2
Memory test circuit, memory array, and testing method of memory array
Jui-Jen Wu, Hsinchu (TW); Jen-Chieh Liu, Hsinchu (TW); Yi-Lun Lu, New Taipei (TW); Win-San Khwa, Taipei (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 1, 2022, as Appl. No. 17/901,801.
Prior Publication US 2024/0079080 A1, Mar. 7, 2024
Int. Cl. G11C 29/50 (2006.01); G11C 7/24 (2006.01); G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 7/24 (2013.01); G11C 29/1201 (2013.01); G11C 29/12015 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/1206 (2013.01); G11C 2029/5002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory test circuit, disposed in a memory array, wherein the memory test circuit comprises:
a test array, comprising a plurality of test cells out of a plurality of memory cells of the memory array;
a write multiplexer, electrically coupled to the test array though a write data line and configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one of the plurality of test cells and the reference voltage is output to a sense amplifier; and
a read multiplexer, electrically coupled to the test array though a read data line and configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one of the plurality of test cells and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.