US 12,171,067 B2
Method of manufacturing printed wiring board
Yoshinori Shimizu, Ageo (JP); Hiroto Iida, Ageo (JP); Misato Mizoguchi, Ageo (JP); Akitoshi Takanashi, Ageo (JP); and Makoto Hosokawa, Ageo (JP)
Assigned to MITSUI MINING & SMELTING CO., LTD., Tokyo (JP)
Appl. No. 17/442,355
Filed by MITSUI MINING & SMELTING CO., LTD., Tokyo (JP)
PCT Filed Mar. 17, 2020, PCT No. PCT/JP2020/011792
§ 371(c)(1), (2) Date Sep. 23, 2021,
PCT Pub. No. WO2020/196106, PCT Pub. Date Oct. 1, 2020.
Claims priority of application No. 2019-058722 (JP), filed on Mar. 26, 2019.
Prior Publication US 2022/0183158 A1, Jun. 9, 2022
Int. Cl. H05K 3/06 (2006.01); C23C 18/16 (2006.01); C25D 5/02 (2006.01); G03F 7/16 (2006.01); H05K 3/46 (2006.01)
CPC H05K 3/064 (2013.01) [C23C 18/1646 (2013.01); C23C 18/1689 (2013.01); C25D 5/022 (2013.01); G03F 7/16 (2013.01); H05K 3/4661 (2013.01); H05K 2203/0502 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method for manufacturing a printed wiring board, comprising:
(a) providing an insulating substrate comprising a roughened surface;
(b) performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less as measured in accordance with JIS B0601-2001 and a valley portion void volume Vvv of 0.010 μm3/μm2 or more and 0.028 μm3/μm2 or less as measured in accordance with ISO 25178;
(c) laminating a photoresist on the surface of the electroless plating layer;
(d) performing exposure and development on the photoresist to form a resist pattern;
(e) applying electroplating to the electroless plating layer via the resist pattern;
(f) stripping the resist pattern; and
(g) etching away an unnecessary portion of the electroless plating layer exposed by stripping of the resist pattern, to form a wiring pattern,
wherein (a) comprises:
(a-1) providing a surface-treated copper foil having a treated surface having an arithmetic mean waviness Wa of 0.20 μm or more and 0.35 μm or less as measured in accordance with JIS B0601-2001 and a valley portion void volume Vvv of 0.030 μm3/μm2 or more and 0.050 μm3/μm2 or less as measured in accordance with ISO 25178,
(a-2) laminating an insulating substrate on the treated surface of the surface-treated copper foil to transfer a surface profile of the treated surface to a surface of the insulating substrate, and then
(a-3) etching away the surface-treated copper foil to obtain the insulating substrate comprising the roughened surface.