US 12,170,232 B2
Manufacturing method and measurement method of semiconductor structure, andsemiconductor structure
Fangfang Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 11, 2022, as Appl. No. 17/647,654.
Application 17/647,654 is a continuation of application No. PCT/CN2021/111569, filed on Aug. 9, 2021.
Claims priority of application No. 202110484441.3 (CN), filed on Apr. 30, 2021.
Prior Publication US 2022/0352040 A1, Nov. 3, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01)
CPC H01L 22/12 (2013.01) [H01L 29/401 (2013.01); H01L 29/4236 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming multiple gate trenches arranged at intervals on the base; wherein the multiple gate trenches comprise a plurality of first gate trenches and a plurality of second gate trenches, the plurality of first gate trenches and the plurality of second gate trenches are arranged alternately along a first direction, and a width of each of the first gate trenches is different from a width of each of the second gate trenches; and
forming a gate structure in each of the gate trenches, wherein each gate structure comprises a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of conductive layers comprises polysilicon.