CPC H03M 1/468 (2013.01) | 17 Claims |
1. A successive-approximation register, SAR, analog-to-digital converter, ADC, comprising:
a differential input port having a first input configured to receive a first input voltage and a second input configured to receive a second input voltage, of opposite polarity compared with first input voltage;
a reference-voltage port having a first reference-voltage input and a second reference-voltage input, wherein the first reference-voltage input is configured to receive a first reference voltage and the second reference-voltage input is configured to receive a second reference voltage, lower than the first reference voltage;
a capacitive digital-to-analog converter, CDAC, having a differential topology with a first sub circuit comprising a first plurality of capacitors, each connected to a common node of the first sub circuit with a first terminal, and a second sub circuit comprising a second plurality of capacitors, each connected to a common node of the second sub circuit with a first terminal, wherein
for each capacitor of the first plurality of capacitors, the first sub circuit comprises:
a first switch connected between the first input of the SAR ADC and a second terminal of that capacitor;
a second switch connected between the first reference-voltage input and the second terminal of that capacitor;
a third switch connected between the second reference-voltage input and the second terminal of that capacitor; and
a capacitive device connected between the second input of the SAR ADC and the second terminal of that capacitor; and
for each capacitor of the second plurality of capacitors, the second sub circuit comprises:
a first switch connected between the second input of the SAR ADC and a second terminal of that capacitor;
a second switch connected between the second reference-voltage input and the second terminal of that capacitor;
a third switch connected between the first reference-voltage input and the second terminal of that capacitor; and
a capacitive device connected between the first input of the SAR ADC and the second terminal of that capacitor.
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