US 12,170,202 B2
Formation and in-situ etching processes for metal layers
Po-Yu Lin, Yilan County (TW); Chi-Yu Chou, Zhubei (TW); Hsien-Ming Lee, Changhua (TW); Huai-Tei Yang, Hsinchu (TW); Chun-Chieh Wang, Kaohsiung (TW); Yueh-Ching Pai, Taichung (TW); Chi-Jen Yang, New Taipei (TW); Tsung-Ta Tang, Hsinchu (TW); and Yi-Ting Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 2, 2023, as Appl. No. 18/149,129.
Application 17/128,408 is a division of application No. 16/729,725, filed on Dec. 30, 2019, granted, now 10,872,769, issued on Dec. 22, 2020.
Application 18/149,129 is a continuation of application No. 17/128,408, filed on Dec. 21, 2020, granted, now 11,545,363.
Application 16/729,725 is a continuation of application No. 16/117,234, filed on Aug. 30, 2018, granted, now 10,535,523, issued on Jan. 14, 2020.
Prior Publication US 2023/0141521 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01)
CPC H01L 21/28088 (2013.01) [H01L 21/28556 (2013.01); H01L 21/32135 (2013.01); H01L 29/4966 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a barrier layer comprising first and second sublayers, wherein a first metal element is disposed at an interface between the first and second sublayers;
a work function layer on the barrier layer and comprising a second metal element; and
a metal layer on the work function layer.