US 12,171,103 B1
Multi-input threshold gate having stacked and folded non-planar capacitors
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Debo Olaosebikan, San Francisco, CA (US); Tanay Gosavi, Portland, OR (US); Noriyuki Sato, Hillsboro, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 14, 2022, as Appl. No. 17/654,764.
Application 17/654,764 is a continuation of application No. 17/653,811, filed on Mar. 7, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor, wherein the first capacitor has a first terminal to receive a first input, and a second terminal coupled to a node;
a second capacitor, wherein the second capacitor has a first terminal to receive a second input, and a second terminal coupled to the node;
a third capacitor, wherein the third capacitor has a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor are non-planar capacitors that are arranged in a stacked and folded configuration, wherein the first capacitor is on a first side of the node, where the third capacitor is on a second side of the node, the second side being laterally opposite to the first side, and wherein the second capacitor is on the first side of the node and vertically above the first capacitor;
a first conductive electrode directly connected to the node, wherein the first conductive electrode extends vertically away from the node; and
a second conductive electrode directly connected to the node, wherein the second conductive electrode extends vertically away from the node, and wherein the first conductive electrode and the second conductive electrode are substantially parallel.