US 12,170,230 B2
Methods of forming bottom dielectric isolation layers
SanKuei Lin, Los Gatos, CA (US); and Pradeep K. Subrahmanyan, Cupertino, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Nov. 20, 2021, as Appl. No. 17/531,726.
Claims priority of provisional application 63/230,806, filed on Aug. 8, 2021.
Prior Publication US 2023/0037719 A1, Feb. 9, 2023
Int. Cl. H01L 21/76 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 29/15 (2006.01)
CPC H01L 21/823807 (2013.01) [H01L 29/66545 (2013.01); H01L 21/76829 (2013.01); H01L 21/823878 (2013.01); H01L 29/154 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A processing method for removing a dummy material, the method comprising:
forming a liner over a superlattice structure on a dummy material, the superlattice structure comprising a plurality of channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs extending between a source trench and a drain trench, the semiconductor material layers comprising silicon (Si), the channel layers comprising of silicon-germanium (SiGe), and the dummy material comprising silicon doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, the concentration of dopant in a range of from 2 atomic percent to 10 atomic percent;
removing the liner from the dummy material; and
removing the dummy material without substantially affecting the channel layers and the semiconductor material layers covered by the liner.