US 12,170,205 B2
Methods for fabricating semiconductor structures
Yi-Nien Su, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 12, 2021, as Appl. No. 17/400,371.
Prior Publication US 2023/0045826 A1, Feb. 16, 2023
Int. Cl. H01L 21/311 (2006.01); H01L 21/033 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/31144 (2013.01) [H01L 21/0332 (2013.01); H01L 21/0334 (2013.01); H01L 21/0337 (2013.01); H01L 21/76897 (2013.01)] 20 Claims
OG exemplary drawing
 
6. A method for fabricating a semiconductor structure, comprising:
depositing a hard mask stack, wherein the hard mask stack comprises:
a first hard mask layer;
a second hard mask layer disposed on the first hard mask layer; and
a third hard mask layer disposed on the second hard mask layer, wherein the third hard mask layer comprises a nitride; and
forming a plurality of mandrels on the hard mask stack;
forming spacer mandrels on sidewall of the plurality of mandrels, wherein the spacer mandrels comprise an oxide;
removing the plurality of mandrels;
etching the third hard mask layer using the spacer mandrels as an etching mask;
forming a via pattern over the first hard mask layer and a dielectric layer under the first hard mask layer; and then
etching through the first hard mask layer and an upper portion of the dielectric layer using the third hard mask layer as an etching mask to form a line pattern in the upper portion of the dielectric layer.