CPC G06F 7/49942 (2013.01) [G06F 7/4991 (2013.01); G06F 7/501 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06G 7/16 (2013.01)] | 5 Claims |
1. A multiplier circuit comprising:
a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor; and
a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor,
wherein a gate of the first transistor is electrically connected to one electrode of the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the other electrode of the first capacitor,
wherein a gate of the second transistor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the one electrode of the second capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,
wherein a gate of the third transistor is electrically connected to one electrode of the third capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the other electrode of the third capacitor,
wherein a gate of the fourth transistor is electrically connected to one electrode of the fourth capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the one electrode of the fourth capacitor, and
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.
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