CPC G06F 9/3861 (2013.01) [G06F 8/4435 (2013.01); G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/382 (2013.01); G06F 9/5016 (2013.01)] | 22 Claims |
1. An apparatus comprising:
decoder circuitry to decode an instruction to load data into a register, the instruction to include a field for an opcode to indicate a protected load operation, a source field for source memory address information, and a destination field to identify a destination register;
memory to store an allocate load-protect (LP) data structure to store an entry for the identified destination register, the entry to comprise (a) an instruction pointer (IP) field to store an IP for the instruction and (b) a status field to indicate when the entry has active status; and
load elision circuitry to:
in response to decoding of the instruction from the IP, use the allocate LP data structure to determine whether the identified destination register has active status for the IP;
in response to determining that the identified destination register has active status for the IP, cause the instruction to be elided; and
in response to determining that the identified destination register does not have active status for the IP, cause the instruction to be executed.
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