CPC G06F 12/0246 (2013.01) [G06F 3/0608 (2013.01); G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01); G06F 12/0884 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |
1. A device, comprising:
memory; and
a controller coupled to the memory and configured to:
generate, in the memory, a first logical address map and a second logical address map that is identical to the first logical address map;
identify the first logical address map as active to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses;
implement one or more changes in the second logical address map while the first logical address map is identified as active; and
identify, after the one or more changes, the second logical address map as active to cause the second logical address map to be loaded in response to a request to load from the memory a map for logical addresses.
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