US 12,169,453 B2
Namespace change propagation in non-volatile memory devices
Alex Frolikov, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 23, 2023, as Appl. No. 18/340,756.
Application 18/340,756 is a continuation of application No. 17/308,558, filed on May 5, 2021, granted, now 11,687,446.
Application 17/308,558 is a continuation of application No. 16/236,897, filed on Dec. 31, 2018, granted, now 11,003,576, issued on May 11, 2021.
Application 16/236,897 is a continuation of application No. 15/814,634, filed on Nov. 16, 2017, granted, now 10,223,254, issued on Mar. 5, 2019.
Prior Publication US 2023/0409473 A1, Dec. 21, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0884 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 3/0608 (2013.01); G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01); G06F 12/0884 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
memory; and
a controller coupled to the memory and configured to:
generate, in the memory, a first logical address map and a second logical address map that is identical to the first logical address map;
identify the first logical address map as active to cause the first logical address map to be loaded in response to a request to load from the memory a map for logical addresses;
implement one or more changes in the second logical address map while the first logical address map is identified as active; and
identify, after the one or more changes, the second logical address map as active to cause the second logical address map to be loaded in response to a request to load from the memory a map for logical addresses.