US 12,170,207 B2
Stacked semiconductor devices and methods of forming same
Hsien-Wei Chen, Hsinchu (TW); Der-Chyang Yeh, Hsinchu (TW); and Li-Hsien Huang, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,460.
Application 16/227,697 is a division of application No. 14/788,258, filed on Jun. 30, 2015, granted, now 10,163,661, issued on Dec. 25, 2018.
Application 18/447,460 is a continuation of application No. 17/876,300, filed on Jul. 28, 2022, granted, now 11,823,912.
Application 17/876,300 is a continuation of application No. 17/101,608, filed on Nov. 23, 2020, granted, now 11,430,670, issued on Aug. 30, 2022.
Application 17/101,608 is a continuation of application No. 16/670,123, filed on Oct. 31, 2019, granted, now 10,847,383, issued on Nov. 24, 2020.
Application 16/670,123 is a continuation of application No. 16/227,697, filed on Dec. 20, 2018, granted, now 10,510,562, issued on Dec. 17, 2019.
Prior Publication US 2023/0386864 A1, Nov. 30, 2023
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 21/563 (2013.01) [H01L 23/3171 (2013.01); H01L 23/3185 (2013.01); H01L 24/00 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 25/0657 (2013.01); H01L 23/3192 (2013.01); H01L 24/81 (2013.01); H01L 25/105 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/034 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/0508 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/0616 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/94 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1047 (2013.01); H01L 2225/1058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a die disposed over a first substrate, the die comprising:
a second substrate comprising an integrated circuit;
contact pads disposed over the second substrate, the contact pads being electrically connected to the integrated circuit, the contact pads comprising a first contact pad, a second contact pad, and a third contact pad;
conductive pillars disposed over and electrically connected to the contact pads, the conductive pillars comprising a first conductive pillar, a second conductive pillar, and a third conductive pillar;
a conductive line over the second substrate, the conductive line being a continuous material with the first conductive pillar and the second conductive pillar, an upper surface of the conductive line being level with an upper surface of the first conductive pillar and an upper surface of the second conductive pillar;
dielectric layers disposed over the second substrate, the dielectric layers disposed over and around the contact pads, the conductive pillars, and the conductive line;
an encapsulant disposed over the first substrate and around lateral edges of the die; and
a redistribution layer disposed over the die, the redistribution layer electrically connected to the conductive pillars.