US 12,170,281 B2
Semiconductor device and method of fabricating the same
Sun Ki Min, Seoul (KR); and Na Rae Oh, Bucheon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 29, 2022, as Appl. No. 17/706,815.
Claims priority of application No. 10-2021-0118783 (KR), filed on Sep. 7, 2021.
Prior Publication US 2023/0070925 A1, Mar. 9, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first active pattern, which is extended in a first direction, on a substrate;
a second active pattern, which is extended in the first direction and spaced apart from the first active pattern in a second direction, on the substrate;
a field insulating layer between the first active pattern and the second active pattern on the substrate;
a first gate electrode on the first active pattern;
a second gate electrode on the second active pattern;
a gate isolation structure separating the first gate electrode and the second gate electrode from each other on the field insulating layer; and
a gate insulating layer between the first gate electrode and the first active pattern,
wherein the gate isolation structure comprises a lower isolation pattern which is in contact with the field insulating layer, and an upper isolation pattern on the lower isolation pattern,
wherein the lower isolation pattern comprises a first portion, and a second portion below the first portion,
wherein in the first portion of the lower isolation pattern, a width of the lower isolation pattern in the second direction increases in a downward direction from the upper isolation pattern,
wherein in the second portion of the lower isolation pattern, a width of the lower isolation pattern in the second direction decreases in the downward direction from the upper isolation pattern, and
wherein the gate insulating layer extends along a sidewall of the lower isolation pattern to a level of an upper surface of the lower isolation pattern.