US 12,171,061 B2
Semiconductor apparatus with inspection terminals
Kyosuke Shibata, Nagano (JP); and Toru Matsuyama, Nagano (JP)
Assigned to Seiko Epson Corporation, Tokyo (JP)
Filed by SEIKO EPSON CORPORATION, Tokyo (JP)
Filed on Feb. 25, 2021, as Appl. No. 17/184,681.
Claims priority of application No. 2020-031814 (JP), filed on Feb. 27, 2020.
Prior Publication US 2021/0274643 A1, Sep. 2, 2021
Int. Cl. H05K 1/02 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01)
CPC H05K 1/029 (2013.01) [H01L 23/49816 (2013.01); H05K 1/0268 (2013.01); H05K 1/0287 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10212 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor apparatus comprising:
a memory controller;
a CPU;
a high-speed communication controller;
a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller;
a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller;
a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and
a terminal mounting surface at which a plurality of coupling terminals including the plurality of memory operation terminals, the plurality of high-speed communication terminals, and the plurality of inspection terminals are distant from each other in first and second directions of the terminal mounting surface that perpendicularly intersect with each other and the plurality of inspection terminals are arranged to receive JTAG (Joint Test Action Group) standard signals, wherein
the terminal mounting surface includes a first side, a second side located facing the first side, a third side intersecting both the first side and the second side, and a fourth side located facing the third side,
the plurality of coupling terminals include a first terminal row located adjacent to the third side and arranged from the first side toward the second side to extend along the first direction of the terminal mounting surface,
the first terminal row includes a first inspection terminal among the plurality of inspection terminals,
the first inspection terminal is located closest to the first side in the first terminal row, and
the first inspection terminal is arranged relative to at least one of the plurality of high-speed communication terminals in the second direction of the terminal mounting surface, and is arranged relative to at least one of the plurality of memory operation terminals in the first direction of the terminal mounting surface.