CPC G06F 13/4282 (2013.01) | 18 Claims |
1. A method of communicating audio data by a serial bus interface, comprising:
outputting a first word select (WS) signal based on direct digital synthesis (DDS) of a clock signal using a frequency control word, the first WS signal periodically transitioning between a low logic state and a high logic state based on the clock signal having a first frequency so that each transition of the first WS signal is aligned with a respective edge of the clock signal;
biasing the frequency control word so that the first WS signal transitions from the low logic state to the high logic state at a desired frequency over a threshold duration, the first frequency being a non-integer multiple of the desired frequency; and
outputting a series of data frames associated with the first WS signal, over a serial bus, for at least the threshold duration.
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