CPC G11C 29/50004 (2013.01) [G11C 29/028 (2013.01)] | 23 Claims |
1. A method comprising:
performing a plurality of at-speed fault detection scan operations of a memory system at a respective plurality of voltage values, wherein each of the plurality of at-speed fault detection scan operations captures timing errors at an elevated frequency value or a lowered voltage value than scan operations performed not at-speed;
causing data gathered from each of the plurality of at-speed fault detection scan operations to be entered into a database, wherein the entered data is associated with the plurality of voltage values;
determining a particular voltage value of the respective plurality of voltage values at which a parameter of the memory system reaches an error quantity or rate threshold; and
indicating the determined particular voltage in the database to be used for performing one or more operations using the memory system.
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