CPC H10B 43/27 (2023.02) [G11C 7/18 (2013.01); H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
1. A semiconductor device comprising:
gate stacks on a substrate and spaced apart from each other in a first direction parallel to an upper surface of the substrate, the gate stacks comprising electrodes and cell insulating layers that are alternately stacked, the substrate comprising a cell array region and a connection region adjacent to the cell array region in a second direction parallel to the upper surface of the substrate and crossing the first direction;
a separation structure between the gate stacks and extending in the second direction;
vertical structures penetrating the gate stacks and having vertical semiconductor patterns extending in a third direction perpendicular to the upper surface of the substrate and conductive pads directly connected to upper surfaces of the vertical semiconductor patterns;
a supporting structure on the gate stacks, the supporting structure extending from the cell array region into the connection region;
bit lines on the supporting structure; and
contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures, the contact plugs directly connected to upper surfaces of the conductive pads,
wherein a bottom surface of a portion of the supporting structure on an upper surface of the separation structure is lower than top surfaces of the conductive pads.
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